Verification of programs using Code Segments and Data Segments

Yasutaka Higa

研究目的

研究内容

近況報告

Overview: Principles of Model Checker

1: System Verification

2: Modeling Concurrent Systems

Figure: Transition System

2: Modeling Concurrent Systems

3: Liner-Time Properties

4: Regular Properties

5: Liner Temporal Logic

5: Liner Temporal Logic

5: Liner Temporal Logic

6: Computation Tree Logic

7: Equivalences and Abstraction

8: Partial Order Reduction

現状検証するべき condition

命題の記述に何を採用するか

CbC をどうやって Transition System に変更にするか

課題