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view a13/smv/test6.smv @ 407:c7ad8d2dc157

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safe halt.agda
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Thu, 09 Nov 2023 18:04:55 +0900
parents 0e8a0e50ed26
children
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MODULE main
 VAR
   gate1 : inverter(gate3.output);
   gate2 : inverter(gate1.output);
   gate3 : inverter(gate2.output);
MODULE inverter(input)
 VAR
   output : boolean;
 INIT
   output = FALSE
 TRANS
   next(output) = !input | next(output) = output