annotate level2/modules/xacia.asm @ 305:1ecde21f77f7

Added IDE target
author boisy
date Mon, 22 Jul 2002 23:14:27 +0000
parents d603059f2b9a
children b3bfa479f8d0
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1 ********************************************************************
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2 * XACIA - Enhanced 6551 driver
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3 *
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4 * $Id$
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5 *
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6 * Ed. Comments Who YY/MM/DD
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7 * ------------------------------------------------------------------
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8 * 10 Bruce Isted distribution version BRI
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9
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10 nam XACIA
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11 ttl Enhanced 6551 driver
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12
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13 ifp1
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14 use defsfile
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15 use scfdefs
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16 endc
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17
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18 * miscellaneous definitions
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19 DCDStBit equ %00100000 DCD status bit for SS.CDSta call
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20 DSRStBit equ %01000000 DSR status bit for SS.CDSta call
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21 Edtn equ 10
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22 Vrsn equ 1
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23
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24 * conditional assembly flags
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25 *A6551 set true 6551 SACIA version
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26 *A6552 set false 65C52 DACIA version
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27 SlpBreak set TkPerSec/2+1 line Break duration
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28 SlpHngUp set TkPerSec/4+1 hang up (drop DTR) duration
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29
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30 ifeq A6552-true
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31 nam DACIA
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32 ttl 65C52 Dual ACIA driver
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33 else
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34
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35 ifeq A6551-true
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36 nam SACIA
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37 ttl 6551 Single ACIA driver
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38 endc
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39 endc
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40
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41 ifeq A6552-true
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42 * 65C52 register definitions
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43 org 0
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44 ISReg rmb 1 IRQ Status (read only)
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45 IEReg equ ISReg IRQ Enable (write only)
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46 CSReg rmb 1 Control Status (read only)
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47 CFReg equ CSReg Control/Format (write only)
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48 CDReg rmb 1 Compare Data (write only, unused in this driver)
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49 TBReg equ CDReg Transmit Break (write only)
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50 DataReg rmb 1 receive/transmit Data (read Rx / write Tx)
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51
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52 * IRQ Status/Enable bit definitions
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53 ISE.IRQ equ %10000000 IRQ occurred/enable
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54 ISE.TxE equ %01000000 Tx data register Empty
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55 ISE.CTS equ %00100000 CTS transition
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56 ISE.DCD equ %00010000 DCD transition
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57 ISE.DSR equ %00001000 DSR transition
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58 ISE.FOB equ %00000100 Rx data Framing or Overrun error, or Break
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59 ISE.Par equ %00000010 Rx data Parity error
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60 ISE.RxF equ %00000001 Rx data register Full
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61
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62 ISE.Errs equ ISE.FOB!ISE.Par IRQ Status error bits
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63 ISE.Flip equ $00 all ISR bits active when set
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64 ISE.Mask equ ISE.CTS!ISE.DCD!ISE.DSR!ISE.FOB!ISE.Par!ISE.RxF active IRQs
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65
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66 * Control Status bit definitions
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67 CS.Frame equ %10000000 framing error (set=error)
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68 CS.TxE equ %01000000 Tx data empty (set=empty)
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69 CS.CTS equ %00100000 CTS input (set=disabled)
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70 CS.DCD equ %00010000 DCD input (set=disabled)
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71 CS.DSR equ %00001000 DSR input (set=disabled)
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72 CS.Break equ %00000100 Rx line break (set=received break)
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73 CS.DTR equ %00000010 DTR output (set=disabled)
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74 CS.RTS equ %00000001 RTS output (set=disabled)
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75
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76 * Control bit definitions
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77 C.TBRCDR equ %01000000 Tx Break/Compare Data register access (set=Tx Break)
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78 C.StpBit equ %00100000 stop bits (set=two, clear=one)
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79 C.Echo equ %00010000 local echo (set=activated)
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80 C.Baud equ %00001111 see baud rate table below
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81
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82 * baud rate table
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83 org 0
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84 BR.00050 rmb 1 50 baud (not supported)
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85 BR.00110 rmb 1 109.92 baud
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86 BR.00135 rmb 1 134.58 baud (not supported)
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87 BR.00150 rmb 1 150 baud (not supported)
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88 BR.00300 rmb 1 300 baud
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89 BR.00600 rmb 1 600 baud
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90 BR.01200 rmb 1 1200 baud
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91 BR.01800 rmb 1 1800 baud (not supported)
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92 BR.02400 rmb 1 2400 baud
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93 BR.03600 rmb 1 3600 baud (not supported)
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94 BR.04800 rmb 1 4800 baud
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95 BR.07200 rmb 1 7200 baud (not supported)
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96 BR.09600 rmb 1 9600 baud
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97 BR.19200 rmb 1 19200 baud
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98 BR.38400 rmb 1 38400 baud
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99 BR.ExClk rmb 1 external Rx and Tx clocks (not supported)
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100
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101 * Format bit definitions
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102 F.Slct equ %10000000 register select (set=Format, clear=Control)
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103 F.DatBit equ %01100000 see data bit table below
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104 F.Par equ %00011100 see parity table below
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105 F.DTR equ %00000010 DTR output (set=disabled)
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106 F.RTS equ %00000001 RTS output (set=disabled)
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107
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108 * data bit table
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109 DB.5 equ %00000000 five data bits per character
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110 DB.6 equ %00100000 six data bits per character
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111 DB.7 equ %01000000 seven data bits per character
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112 DB.8 equ %01100000 eight data bits per character
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113
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114 * parity table
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115 Par.None equ %00000000
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116 Par.Odd equ %00000100
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117 Par.Even equ %00001100
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118 Par.Mark equ %00010100
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119 Par.Spac equ %00011100
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120
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121 * Transmit Break bit definitions
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122 TB.Brk equ %00000010 Tx break control (set=transmit continuous line Break)
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123 TB.Par equ %00000001 parity check (set=parity bit to ISE.Par, clear=normal)
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124 else
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125
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126 ifeq A6551-true
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127 * 6551 register definitions
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128 org 0
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129 DataReg rmb 1 receive/transmit Data (read Rx / write Tx)
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130 StatReg rmb 1 status (read only)
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131 PRstReg equ StatReg programmed reset (write only)
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132 CmdReg rmb 1 command (read/write)
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133 CtlReg rmb 1 control (read/write)
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134
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135 * Status bit definitions
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136 Stat.IRQ equ %10000000 IRQ occurred
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137 Stat.DSR equ %01000000 DSR level (clear = active)
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138 Stat.DCD equ %00100000 DCD level (clear = active)
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139 Stat.TxE equ %00010000 Tx data register Empty
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140 Stat.RxF equ %00001000 Rx data register Full
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141 Stat.Ovr equ %00000100 Rx data Overrun error
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142 Stat.Frm equ %00000010 Rx data Framing error
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143 Stat.Par equ %00000001 Rx data Parity error
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144
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145 Stat.Err equ Stat.Ovr!Stat.Frm!Stat.Par Status error bits
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146 Stat.Flp equ $00 all Status bits active when set
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147 Stat.Msk equ Stat.IRQ!Stat.RxF active IRQs
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148
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149 * Control bit definitions
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150 Ctl.Stop equ %10000000 stop bits (set=two, clear=one)
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151 Ctl.DBit equ %01100000 see data bit table below
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152 Ctl.RxCS equ %00010000 Rx clock source (set=baud rate, clear=external)
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153 Ctl.Baud equ %00001111 see baud rate table below
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154
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155 * data bit table
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156 DB.8 equ %00000000 eight data bits per character
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157 DB.7 equ %00100000 seven data bits per character
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158 DB.6 equ %01000000 six data bits per character
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159 DB.5 equ %01100000 five data bits per character
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160
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161 * baud rate table
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162 org $00
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163 BR.ExClk rmb 1 16x external clock (not supported)
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164 org $11
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165 BR.00050 rmb 1 50 baud (not supported)
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166 BR.00075 rmb 1 75 baud (not supported)
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167 BR.00110 rmb 1 109.92 baud
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168 BR.00135 rmb 1 134.58 baud (not supported)
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169 BR.00150 rmb 1 150 baud (not supported)
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170 BR.00300 rmb 1 300 baud
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171 BR.00600 rmb 1 600 baud
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172 BR.01200 rmb 1 1200 baud
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173 BR.01800 rmb 1 1800 baud (not supported)
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174 BR.02400 rmb 1 2400 baud
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175 BR.03600 rmb 1 3600 baud (not supported)
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176 BR.04800 rmb 1 4800 baud
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177 BR.07200 rmb 1 7200 baud (not supported)
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178 BR.09600 rmb 1 9600 baud
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179 BR.19200 rmb 1 19200 baud
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180
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181 * Command bit definitions
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182 Cmd.Par equ %11100000 see parity table below
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183 Cmd.Echo equ %00010000 local echo (set=activated)
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184 Cmd.TIRB equ %00001100 see Tx IRQ/RTS/Break table below
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185 Cmd.RxI equ %00000010 Rx IRQ (set=disabled)
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186 Cmd.DTR equ %00000001 DTR output (set=enabled)
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187
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188 * parity table
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189 Par.None equ %00000000
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190 Par.Odd equ %00100000
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191 Par.Even equ %01100000
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192 Par.Mark equ %10100000
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193 Par.Spac equ %11100000
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194
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195 * Tx IRQ/RTS/Break table
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196 TIRB.Off equ %00000000 RTS & Tx IRQs disabled
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197 TIRB.On equ %00000100 RTS & Tx IRQs enabled
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198 TIRB.RTS equ %00001000 RTS enabled, Tx IRQs disabled
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199 TIRB.Brk equ %00001100 RTS enabled, Tx IRQs disabled, Tx line Break
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200 endc
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201 endc
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202
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203 * V.ERR bit definitions
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204 DCDLstEr equ %00100000 DCD lost error
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205 OvrFloEr equ %00000100 Rx data overrun or Rx buffer overflow error
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206 FrmingEr equ %00000010 Rx data framing error
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207 ParityEr equ %00000001 Rx data parity error
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208
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209 * FloCtlRx bit definitions
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210 FCRxSend equ %10000000 send flow control character
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211 FCRxSent equ %00010000 Rx disabled due to XOFF sent
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212 FCRxDTR equ %00000010 Rx disabled due to DTR
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213 FCRxRTS equ %00000001 Rx disabled due to RTS
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214
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diff changeset
215 * FloCtlTx bit definitions
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diff changeset
216 FCTxXOff equ %10000000 due to XOFF received
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diff changeset
217 FCTxBrk equ %00000010 due to currently transmitting Break
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diff changeset
218
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diff changeset
219 * Wrk.Type bit definitions
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diff changeset
220 Parity equ %11100000 parity bits
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diff changeset
221 MdmKill equ %00010000 modem kill option
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diff changeset
222 RxSwFlow equ %00001000 Rx data software (XON/XOFF) flow control
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parents:
diff changeset
223 TxSwFlow equ %00000100 Tx data software (XON/XOFF) flow control
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parents:
diff changeset
224 RTSFlow equ %00000010 CTS/RTS hardware flow control
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parents:
diff changeset
225 DSRFlow equ %00000001 DSR/DTR hardware flow control
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diff changeset
226
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diff changeset
227 * Wrk.Baud bit definitions
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parents:
diff changeset
228 StopBits equ %10000000 number of stop bits code
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diff changeset
229 WordLen equ %01100000 word length code
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diff changeset
230 BaudRate equ %00001111 baud rate code
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diff changeset
231
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diff changeset
232 * Wrk.XTyp bit definitions
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diff changeset
233 SwpDCDSR equ %10000000 swap DCD+DSR bits (valid for 6551 only)
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diff changeset
234 ForceDTR equ %01000000 don't drop DTR in term routine
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diff changeset
235 RxBufPag equ %00001111 input buffer page count
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236
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parents:
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237 * static data area definitions
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238 org V.SCF allow for SCF manager data area
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239
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240 ifeq A6552-true
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241 Cpy.CR rmb 1 Control register copy (MUST immediately precede Cpy.FR)
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parents:
diff changeset
242 Cpy.FR rmb 1 Format register copy (MUST immediately follow Cpy.CR)
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diff changeset
243 Cpy.ISR rmb 1 IRQ Status register copy (MUST immediately precede Cpy.CSR)
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diff changeset
244 Cpy.CSR rmb 1 Control Status register copy (MUST immediately follow Cpy.ISR)
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245 else
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246
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247 ifeq A6551-true
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248 Cpy.Stat rmb 1 Status register copy
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249 CpyDCDSR rmb 1 DSR+DCD status copy
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250 Mask.DCD rmb 1 DCD status bit mask (MUST immediately precede Mask.DSR)
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251 Mask.DSR rmb 1 DSR status bit mask (MUST immediately follow Mask.DCD)
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252 endc
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253 endc
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254
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255 CDSigPID rmb 1 process ID for CD signal
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256 CDSigSig rmb 1 CD signal code
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257 FloCtlRx rmb 1 Rx flow control flags
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258 FloCtlTx rmb 1 Tx flow control flags
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259 RxBufEnd rmb 2 end of Rx buffer
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260 RxBufGet rmb 2 Rx buffer output pointer
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261 RxBufMax rmb 2 Send XOFF (if enabled) at this point
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262 RxBufMin rmb 2 Send XON (if XOFF sent) at this point
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263 RxBufPtr rmb 2 pointer to Rx buffer
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264 RxBufPut rmb 2 Rx buffer input pointer
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265 RxBufSiz rmb 2 Rx buffer size
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266 RxDatLen rmb 2 current length of data in Rx buffer
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267 SigSent rmb 1 keyboard abort/interrupt signal already sent
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268 SSigPID rmb 1 SS.SSig process ID
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269 SSigSig rmb 1 SS.SSig signal code
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270 WritFlag rmb 1 initial write attempt flag
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271 Wrk.Type rmb 1 type work byte (MUST immediately precede Wrk.Baud)
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diff changeset
272 Wrk.Baud rmb 1 baud work byte (MUST immediately follow Wrk.Type)
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273 Wrk.XTyp rmb 1 extended type work byte
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274 RxBufDSz equ 256-. default Rx buffer gets remainder of page...
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275 RxBuff rmb RxBufDSz default Rx buffer
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276 MemSize equ .
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277
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278 mod ModSize,ModName,Drivr+Objct,ReEnt+Vrsn,ModEntry,MemSize
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279
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280 fcb UPDAT. access mode(s)
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281
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282 ifeq A6552-true
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283 ModName fcs "DACIA"
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284 else
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285
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286 ifeq A6551-true
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287 ModName fcs "SACIA"
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288 endc
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289 endc
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290
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291 fcb Edtn
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292
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293 SlotSlct fcb MPI.Slot selected MPI slot
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294
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295 ModEntry equ *
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296 lbra Init
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297 lbra Read
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298 lbra Writ
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299 lbra GStt
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300 lbra SStt
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301 lbra Term
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diff changeset
302
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parents:
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303 IRQPckt equ *
6641a883d6b0 Initial revision
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parents:
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304
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parents:
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305 ifeq A6552-true
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parents:
diff changeset
306 Pkt.Flip fcb ISE.Flip D.Poll flip byte
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307 Pkt.Mask fcb ISE.Mask D.Poll mask byte
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308 else
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309
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310 ifeq A6551-true
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diff changeset
311 Pkt.Flip fcb Stat.Flp flip byte
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312 Pkt.Mask fcb Stat.Msk mask byte
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313 endc
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parents:
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314 endc
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315
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316 fcb $0A priority
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diff changeset
317
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318 BaudTabl equ *
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diff changeset
319
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320 ifeq A6552-true
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321 fcb BR.00110,BR.00300,BR.00600
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diff changeset
322 fcb BR.01200,BR.02400,BR.04800
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diff changeset
323 fcb BR.09600,BR.19200,BR.38400
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diff changeset
324 else
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parents:
diff changeset
325
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326 ifeq A6551-true
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diff changeset
327 fcb BR.00110,BR.00300,BR.00600
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diff changeset
328 fcb BR.01200,BR.02400,BR.04800
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diff changeset
329 fcb BR.09600,BR.19200
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330 endc
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331 endc
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332
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333
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334 * NOTE: SCFMan has already cleared all device memory except for V.PAGE and
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335 * V.PORT. Zero-default variables are: CDSigPID, CDSigSig, Wrk.XTyp.
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336 Init equ *
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337 clrb default to no error...
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338 pshs cc,b,dp save IRQ/Carry status, dummy B, system DP
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339 lbsr SetDP go set our DP
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340 pshs y save descriptor pointer
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341 ldd <V.PORT base hardware address
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diff changeset
342
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343 ifeq A6552-true
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344 else
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parents:
diff changeset
345
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346 ifeq A6551-true
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347 addd #1 point to 6551 status address
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348 endc
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349 endc
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diff changeset
350
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parents:
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351 leax IRQPckt,pcr
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352 leay IRQSvc,pcr
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353 os9 F$IRQ
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354 puls y recover descriptor pointer
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355 lbcs ErrExit go report error...
6641a883d6b0 Initial revision
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diff changeset
356 ldb M$Opt,y get option size
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parents:
diff changeset
357 cmpb #IT.XTYP-IT.DTP room for extended type byte?
6641a883d6b0 Initial revision
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358 bls DfltInfo no, go use defaults...
6641a883d6b0 Initial revision
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parents:
diff changeset
359
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diff changeset
360 ifeq A6552-true
6641a883d6b0 Initial revision
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parents:
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361 else
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parents:
diff changeset
362
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diff changeset
363 ifeq A6551-true
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parents:
diff changeset
364 ldd #Stat.DCD*256+Stat.DSR default (unswapped) DCD+DSR masks
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parents:
diff changeset
365 tst IT.XTYP,y check extended type byte for swapped DCD & DSR bits
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parents:
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366 bpl NoSwap no, go skip swapping them...
6641a883d6b0 Initial revision
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parents:
diff changeset
367 exg a,b swap to DSR+DCD masks
6641a883d6b0 Initial revision
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368 NoSwap std <Mask.DCD save DCD+DSR (or DSR+DCD) masks
6641a883d6b0 Initial revision
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parents:
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369 endc
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parents:
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370 endc
6641a883d6b0 Initial revision
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parents:
diff changeset
371
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parents:
diff changeset
372 lda IT.XTYP,y get extended type byte
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diff changeset
373 sta <Wrk.XTyp save it
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374 anda #RxBufPag clear all but Rx buffer page count bits
6641a883d6b0 Initial revision
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375 beq DfltInfo none, go use defaults...
6641a883d6b0 Initial revision
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parents:
diff changeset
376 clrb make data size an even number of pages
6641a883d6b0 Initial revision
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parents:
diff changeset
377 pshs u save data pointer
6641a883d6b0 Initial revision
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parents:
diff changeset
378 os9 F$SRqMem get extended buffer
6641a883d6b0 Initial revision
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parents:
diff changeset
379 tfr u,x copy address
6641a883d6b0 Initial revision
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parents:
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380 puls u recover data pointer
6641a883d6b0 Initial revision
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parents:
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381 lbcs TermExit error, go remove IRQ entry and exit...
6641a883d6b0 Initial revision
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diff changeset
382 bra SetRxBuf
6641a883d6b0 Initial revision
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parents:
diff changeset
383
6641a883d6b0 Initial revision
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parents:
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384 DfltInfo ldd #RxBufDSz default Rx buffer size
6641a883d6b0 Initial revision
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parents:
diff changeset
385 leax RxBuff,u default Rx buffer address
6641a883d6b0 Initial revision
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parents:
diff changeset
386 SetRxBuf std <RxBufSiz save Rx buffer size
6641a883d6b0 Initial revision
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parents:
diff changeset
387 stx <RxBufPtr save Rx buffer address
6641a883d6b0 Initial revision
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parents:
diff changeset
388 stx <RxBufGet set initial Rx buffer input address
6641a883d6b0 Initial revision
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parents:
diff changeset
389 stx <RxBufPut set initial Rx buffer output address
6641a883d6b0 Initial revision
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parents:
diff changeset
390 leax d,x point to end of Rx buffer
6641a883d6b0 Initial revision
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parents:
diff changeset
391 stx <RxBufEnd save Rx buffer end address
6641a883d6b0 Initial revision
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parents:
diff changeset
392 subd #80 characters available in Rx buffer
6641a883d6b0 Initial revision
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parents:
diff changeset
393 std <RxBufMax set auto-XOFF threshold
6641a883d6b0 Initial revision
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parents:
diff changeset
394 ldd #10 characters remaining in Rx buffer
6641a883d6b0 Initial revision
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parents:
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395 std <RxBufMin set auto-XON threshold after auto-XOFF
6641a883d6b0 Initial revision
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parents:
diff changeset
396
6641a883d6b0 Initial revision
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parents:
diff changeset
397 ifeq A6552-true
6641a883d6b0 Initial revision
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parents:
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398 ldd #C.TBRCDR*256+(F.Slct!F.DTR!F.RTS) [A]=control, [B]=format register
6641a883d6b0 Initial revision
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parents:
diff changeset
399 sta <Cpy.CR save control register copy
6641a883d6b0 Initial revision
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parents:
diff changeset
400 lda <Wrk.XTyp
6641a883d6b0 Initial revision
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parents:
diff changeset
401 anda #ForceDTR forced DTR?
6641a883d6b0 Initial revision
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parents:
diff changeset
402 beq NoDTR no, don't enable DTR yet
6641a883d6b0 Initial revision
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parents:
diff changeset
403 andb #^F.DTR clear (enable) DTR bit
6641a883d6b0 Initial revision
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parents:
diff changeset
404 NoDTR stb <Cpy.FR save format register copy
6641a883d6b0 Initial revision
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parents:
diff changeset
405 else
6641a883d6b0 Initial revision
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parents:
diff changeset
406
6641a883d6b0 Initial revision
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parents:
diff changeset
407 ifeq A6551-true
6641a883d6b0 Initial revision
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parents:
diff changeset
408 ldb #TIRB.RTS default command register
6641a883d6b0 Initial revision
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parents:
diff changeset
409 lda <Wrk.XTyp
6641a883d6b0 Initial revision
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parents:
diff changeset
410 anda #ForceDTR forced DTR?
6641a883d6b0 Initial revision
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parents:
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411 beq NoDTR no, don't enable DTR yet
6641a883d6b0 Initial revision
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parents:
diff changeset
412 orb #Cmd.DTR set (enable) DTR bit
6641a883d6b0 Initial revision
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parents:
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413 NoDTR ldx <V.PORT get port address
6641a883d6b0 Initial revision
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parents:
diff changeset
414 stb CmdReg,x set new command register
6641a883d6b0 Initial revision
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parents:
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415 endc
6641a883d6b0 Initial revision
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parents:
diff changeset
416 endc
6641a883d6b0 Initial revision
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parents:
diff changeset
417
6641a883d6b0 Initial revision
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parents:
diff changeset
418 ldd IT.PAR,y [A] = IT.PAR, [B] = IT.BAU from descriptor
6641a883d6b0 Initial revision
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parents:
diff changeset
419 lbsr SetPort go save it and set up control/format registers
6641a883d6b0 Initial revision
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parents:
diff changeset
420 orcc #IntMasks disable IRQs while setting up hardware
6641a883d6b0 Initial revision
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parents:
diff changeset
421 lda >PIA1Base+3 get PIA CART* input control register
6641a883d6b0 Initial revision
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parents:
diff changeset
422 anda #$FC clear PIA CART* control bits
6641a883d6b0 Initial revision
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parents:
diff changeset
423 sta >PIA1Base+3 disable PIA CART* FIRQs
6641a883d6b0 Initial revision
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parents:
diff changeset
424 lda >PIA1Base+2 clear possible pending PIA CART* FIRQ
6641a883d6b0 Initial revision
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parents:
diff changeset
425 lda #$01 GIME CART* IRQ bit
6641a883d6b0 Initial revision
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parents:
diff changeset
426 ora >D.IRQER mask in current GIME IRQ enables
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
427 sta >D.IRQER save GIME CART* IRQ enable shadow register
6641a883d6b0 Initial revision
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parents:
diff changeset
428 sta >IrqEnR enable GIME CART* IRQs
6641a883d6b0 Initial revision
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parents:
diff changeset
429
6641a883d6b0 Initial revision
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parents:
diff changeset
430 ifeq A6552-true
6641a883d6b0 Initial revision
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parents:
diff changeset
431 lda #ISE.IRQ!ISE.Mask DACIA IRQ enables
6641a883d6b0 Initial revision
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parents:
diff changeset
432 sta IEReg,x enable DACIA IRQs for this port ([X]=V.PORT from SetPort)
6641a883d6b0 Initial revision
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parents:
diff changeset
433 ldb ISReg,x ensure old CTS, DCD, and DSR transition IRQ flags are clear
6641a883d6b0 Initial revision
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parents:
diff changeset
434 ldb DataReg,x ensure old error and Rx data IRQ flags are clear
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
435 ldb ISReg,x ... again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
436 ldb DataReg,x ... and again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
437 ldd ISReg,x get new IRQ and Control status registers
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
438 eora Pkt.Flip,pcr flip bits per D.Poll
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
439 anda Pkt.Mask,pcr any IRQ(s) still pending?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
440 lbne NRdyErr yes, go report error... (device not plugged in?)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
441 std <Cpy.ISR save new IRQ and Control status register copies
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
442 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
443
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
444 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
445 lda StatReg,x ensure old IRQ flags are clear
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
446 lda DataReg,x ensure old error and Rx data IRQ flags are clear
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
447 lda StatReg,x ... again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
448 lda DataReg,x ... and again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
449 lda StatReg,x get new Status register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
450 sta <Cpy.Stat save Status copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
451 tfr a,b copy it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
452 eora Pkt.Flip,pcr flip bits per D.Poll
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
453 anda Pkt.Mask,pcr any IRQ(s) still pending?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
454 lbne NRdyErr yes, go report error... (device not plugged in?)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
455 andb #Stat.DSR!Stat.DCD clear all but DSR+DCD status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
456 stb <CpyDCDSR save new DCD+DSR status copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
457 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
458 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
459
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
460 lda SlotSlct,pcr get MPI slot select value
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
461 bmi NoSelect no MPI slot select, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
462 sta >MPI.Slct set MPI slot select register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
463 NoSelect puls cc,b,dp,pc recover IRQ/Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
464
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
465
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
466 Term equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
467 clrb default to no error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
468 pshs cc,b,dp save IRQ/Carry status, dummy B, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
469 lbsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
470
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
471 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
472 lda #^ISE.IRQ disable all DACIA IRQs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
473 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
474 sta IEReg,x disable DACIA IRQs for this port
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
475 lda <Cpy.FR get format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
476 ora #F.DTR!F.RTS set (disable) DTR and RTS bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
477 ldb <Wrk.XTyp get extended type byte
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
478 andb #ForceDTR forced DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
479 beq KeepDTR no, go leave DTR disabled...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
480 anda #^F.DTR clear (enable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
481 KeepDTR sta CFReg,x set DTR and RTS enable/disable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
482 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
483
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
484 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
485 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
486 lda CmdReg,x get current Command register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
487 anda #^(Cmd.TIRB!Cmd.DTR) disable Tx IRQs, RTS, and DTR
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
488 ora #Cmd.RxI disable Rx IRQs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
489 ldb <Wrk.XTyp get extended type byte
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
490 andb #ForceDTR forced DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
491 beq KeepDTR no, go leave DTR disabled...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
492 ora #Cmd.DTR set (enable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
493 KeepDTR sta CmdReg,x set DTR and RTS enable/disable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
494 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
495 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
496
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
497 ldd <RxBufSiz get Rx buffer size
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
498 tsta less than 256 bytes?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
499 beq TermExit yes, no system memory to return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
500 pshs u save data pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
501 ldu <RxBufPtr get address of system memory
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
502 os9 F$SRtMem
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
503 puls u recover data pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
504 TermExit ldd <V.PORT base hardware address is status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
505
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
506 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
507 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
508
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
509 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
510 addd #1 point to 6551 status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
511 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
512 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
513
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
514 ldx #$0000 remove IRQ table entry
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
515 leay IRQSvc,pcr
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
516 puls cc recover IRQ/Carry status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
517 os9 F$IRQ
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
518 puls a,dp,pc restore dummy A, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
519
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
520
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
521 ReadSlp ldd >D.Proc process descriptor address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
522 sta <V.WAKE save MSB for IRQ service routine
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
523 tfr d,x copy process descriptor address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
524 ldb P$State,x get process state flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
525 orb #Suspend set suspend flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
526 stb P$State,x put process in suspend state
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
527 lbsr Sleep1 go suspend process...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
528 ldx >D.Proc process descriptor address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
529 ldb P$Signal,x pending signal for this process?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
530 beq ChkState no, go check process state...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
531 cmpb #S$Intrpt do we honor signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
532 bls ErrExit yes, go do it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
533 ChkState ldb P$State,x get process state
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
534 bitb #Condem we be dead?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
535 bne PrAbtErr yes, go do it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
536 ldb <V.WAKE true interrupt?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
537 bne ReadSlp no, go suspend again...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
538 ReadLoop puls cc,b,dp recover IRQ/Carry status, dummy B, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
539
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
540 Read equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
541 clrb default to no errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
542 pshs cc,b,dp save IRQ/Carry status, dummy B, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
543 lbsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
544 orcc #IntMasks disable IRQs while checking Rx flow control
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
545 lda <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
546 beq ReadChar none, go get Rx character...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
547 ldx <RxDatLen get Rx data count again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
548 cmpx <RxBufMin at or below XON level?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
549 bhi ReadChar no, go get Rx character...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
550 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
551 bita #FCRxSent Rx disabled due to XOFF sent?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
552 beq ChkHWHS no, go check hardware handshake(s)...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
553 ldb <FloCtlTx get Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
554 bitb #FCTxBrk currently transmitting line Break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
555 bne ReadLoop yes, go skip XON this time...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
556
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
557 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
558 ldb CSReg,x get new Control Status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
559 bitb #CS.TxE Tx data register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
560 beq ReadLoop no, go skip XON this time...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
561 ldb <V.XON
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
562 stb DataReg,x write XON character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
563 ChkHWHS bita #FCRxDTR!FCRxRTS Rx disabled due to DTR or RTS?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
564 beq RxFloClr no, go clear Rx flow control flag(s)...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
565 ldb <Cpy.FR get Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
566 andb #^(F.DTR!F.RTS) clear (enable) DTR and RTS bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
567 stb <Cpy.FR save Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
568 stb CFReg,x set Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
569 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
570
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
571 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
572 ldb StatReg,x get new Status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
573 bitb #Stat.TxE Tx data register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
574 beq ReadLoop no, go skip XON this time...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
575 ldb <V.XON
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
576 stb DataReg,x write XON character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
577 ChkHWHS bita #FCRxDTR!FCRxRTS Rx disabled due to DTR or RTS?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
578 beq RxFloClr no, go clear Rx flow control flag(s)...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
579 ldb CmdReg,x get current Command register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
580 andb #^Cmd.TIRB clear Tx IRQ/RTS/Break control bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
581 orb #TIRB.RTS!Cmd.DTR enable RTS and DTR, disable Tx IRQs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
582 stb CmdReg,x set Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
583 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
584 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
585
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
586 RxFloClr clr <FloCtlRx clear Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
587 ReadChar ldb <V.ERR get accumulated errors, if any
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
588 stb PD.ERR,y set/clear error(s) in path descriptor
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
589 bne ReprtErr error(s), go report it/them...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
590 ldx <RxDatLen get Rx buffer count
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
591 beq ReadSlp none, go sleep while waiting for new Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
592 leax -1,x less character we're about to grab
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
593 stx <RxDatLen save new Rx data count
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
594 ldx <RxBufGet current Rx buffer pickup position
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
595 lda ,x+ get Rx character, set up next pickup position
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
596 cmpx <RxBufEnd end of Rx buffer?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
597 blo SetPckUp no, go keep pickup pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
598 ldx <RxBufPtr get Rx buffer start address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
599 SetPckUp stx <RxBufGet set new Rx data pickup pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
600 puls cc,b,dp,pc recover IRQ/Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
601
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
602
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
603 PrAbtErr ldb #E$PrcAbt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
604 bra ErrExit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
605
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
606 ReprtErr clr <V.ERR clear error status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
607 bitb #DCDLstEr DCD lost error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
608 bne HngUpErr yes, go report it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
609 ldb #E$Read
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
610 ErrExit puls cc restore IRQ enable and Carry status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
611 coma error, set Carry
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
612 puls a,dp,pc restore dummy A (or Tx character), system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
613
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
614 HngUpErr ldb #E$HangUp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
615 lda #PST.DCD DCD lost flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
616 sta PD.PST,y set path status flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
617 bra ErrExit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
618
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
619 NRdyErr ldb #E$NotRdy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
620 bra ErrExit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
621
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
622 UnSvcErr ldb #E$UnkSvc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
623 bra ErrExit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
624
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
625
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
626 WritLoop lda <WritFlag first pass through for this Tx character?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
627 beq WritFast yes, don't sleep yet...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
628 lbsr Sleep1 go sleep for balance of tick...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
629 WritFast inc <WritFlag set "initial write attempt" flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
630 puls cc,a,dp recover IRQ/Carry status, Tx character, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
631
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
632 Writ equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
633 clrb default to no error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
634 pshs cc,a,dp save IRQ/Carry status, Tx character, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
635 lbsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
636 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
637 orcc #IntMasks disable IRQs during error and Tx disable checks
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
638 ldb <V.ERR get accumulated errors, if any
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
639 andb #DCDLstEr DCD lost error? (ignore other errors, if any)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
640 stb PD.ERR,y set/clear error(s) in path descriptor
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
641 bne ReprtErr DCD lost error, go report it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
642
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
643 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
644 ldb <Cpy.CSR get copy of control status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
645 bitb #CS.CTS Tx disabled due to CTS?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
646 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
647 lda <Wrk.Type get software/hardware handshake enables
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
648 bita #DSRFlow DSR/DTR handshake enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
649 beq ChkTxFlo no, go check Tx flow control
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
650 bitb #CS.DSR Tx disabled due to DSR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
651 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
652 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
653
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
654 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
655 lda <Wrk.Type get software/hardware handshake enables
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
656 bita #DSRFlow DSR/DTR handshake enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
657 beq ChkTxFlo no, go check Tx flow control
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
658 ldb <Cpy.Stat get copy of status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
659 bitb <Mask.DSR Tx disabled due to DSR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
660 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
661 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
662 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
663
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
664 ChkTxFlo ldb <FloCtlTx get Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
665 bitb #FCTxBrk currently transmitting line Break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
666 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
667 bita #TxSwFlow Tx software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
668 beq ChkRxFlo no, go check pending Rx flow control
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
669 bitb #FCTxXOff Tx disabled due to received XOFF?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
670 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
671 ChkRxFlo bita #RxSwFlow Rx software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
672 beq ChkTxE no, go check Tx register empty
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
673 ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
674 bitb #FCRxSend XON/XOFF Rx flow control pending?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
675 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
676 ChkTxE lda 1,s get Tx character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
677
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
678 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
679 ldb CSReg,x get new control status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
680 bitb #CS.TxE Tx register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
681 beq WritLoop no, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
682 sta DataReg,x write Tx character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
683 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
684
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
685 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
686 ldb StatReg,x get new status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
687 bitb #Stat.TxE Tx register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
688 beq WritLoop no, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
689 sta DataReg,x write Tx character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
690 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
691 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
692
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
693 clr <WritFlag clear "initial write attempt" flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
694 puls cc,a,dp,pc recover IRQ/Carry status, Tx character, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
695
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
696
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
697 GStt equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
698 clrb default to no error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
699 pshs cc,b,dp save IRQ/Carry status, dummy B, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
700 lbsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
701 ldx PD.RGS,y caller's register stack pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
702 cmpa #SS.EOF
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
703 beq GSExitOK yes, SCF devices never return EOF
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
704 cmpa #SS.Ready
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
705 bne GetScSiz
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
706 ldd <RxDatLen get Rx data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
707 beq NRdyErr none, go report error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
708 tsta more than 255 bytes?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
709 beq SaveLen no, keep Rx data available
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
710 ldb #255 yes, just use 255
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
711 SaveLen stb R$B,x set Rx data available in caller's [B]
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
712 GSExitOK puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
713
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
714 GetScSiz cmpa #SS.ScSiz
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
715 bne GetComSt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
716 ldu PD.DEV,y
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
717 ldu V$DESC,u
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
718 clra
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
719 ldb IT.COL,u
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
720 std R$X,x
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
721 ldb IT.ROW,u
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
722 std R$Y,x
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
723 puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
724
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
725 GetComSt cmpa #SS.ComSt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
726 lbne UnSvcErr no, go report error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
727 ldd <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
728 std R$Y,x
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
729 clra default to DCD and DSR enabled
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
730
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
731 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
732 ldb <Cpy.CSR get current status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
733 bitb #CS.DCD DCD bit set (disabled)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
734 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
735
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
736 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
737 ldb <CpyDCDSR get current DSR+DCD status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
738 bitb <Mask.DCD DCD bit set (disabled)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
739 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
740 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
741
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
742 beq CheckDSR no, go check DSR status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
743 ora #DCDStBit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
744
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
745 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
746 CheckDSR bitb #CS.DSR DSR bit set (disabled)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
747 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
748
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
749 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
750 CheckDSR bitb <Mask.DSR DSR bit set (disabled)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
751 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
752 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
753
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
754 beq SaveCDSt no, go set DCD/DSR status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
755 ora #DSRStBit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
756 SaveCDSt sta R$B,x set 6551 ACIA style DCD/DSR status in caller's [B]
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
757 puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
758
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
759
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
760 BreakSlp ldx #SlpBreak SS.Break duration
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
761 bra TimedSlp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
762 HngUpSlp ldx #SlpHngUp SS.HngUp duration
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
763 bra TimedSlp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
764 Sleep1 ldx #1 give up balance of tick
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
765 TimedSlp pshs cc save IRQ enable status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
766 andcc #Intmasks enable IRQs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
767 os9 F$Sleep
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
768 puls cc,pc restore IRQ enable status, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
769
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
770
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
771 SStt equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
772 clrb default to no error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
773 pshs cc,b,dp save IRQ/Carry status, dummy B, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
774 lbsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
775 ldx PD.RGS,y
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
776 cmpa #SS.HngUp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
777 bne SetBreak
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
778
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
779 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
780 lda #F.DTR set (disable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
781 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
782 orcc #IntMasks disable IRQs while setting Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
783 ora <Cpy.FR mask in Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
784 sta <Cpy.FR save Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
785 sta CFReg,x set new Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
786 bsr HngUpSlp go sleep for a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
787 lda #^(F.DTR!F.RTS) clear (enable) DTR and RTS bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
788 FRegClr ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
789 anda <Cpy.FR mask in Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
790 ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
791 bitb #FCRxDTR Rx disabled due to DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
792 beq LeaveDTR no, go leave DTR enabled
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
793 ora #F.DTR set (disable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
794 LeaveDTR bitb #FCRxRTS Rx disabled due to RTS?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
795 beq LeaveRTS no, go leave RTS enabled
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
796 ora #F.RTS set (disable) RTS bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
797 LeaveRTS sta <Cpy.FR save Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
798 sta CFReg,x set new Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
799 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
800
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
801 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
802 lda #^Cmd.DTR cleared (disabled) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
803 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
804 orcc #IntMasks disable IRQs while setting Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
805 anda CmdReg,x mask in current Command register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
806 sta CmdReg,x set new Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
807 bsr HngUpSlp go sleep for a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
808 BreakClr lda #^(Cmd.TIRB!Cmd.DTR) clear (disable) DTR and RTS control bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
809 FRegClr ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
810 anda CmdReg,x mask in current Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
811 ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
812 bitb #FCRxDTR Rx disabled due to DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
813 bne LeaveDTR yes, go leave DTR disabled
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
814 ora #Cmd.DTR set (enable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
815 LeaveDTR bitb #FCRxRTS Rx disabled due to RTS?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
816 bne LeaveRTS yes, go leave RTS disabled
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
817 ora #TIRB.RTS enable RTS output
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
818 LeaveRTS ldb <FloCtlTx get Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
819 bitb #FCTxBrk currently transmitting line Break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
820 beq NotTxBrk no, go leave RTS alone...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
821 ora #TIRB.Brk set Tx Break bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
822 NotTxBrk sta CmdReg,x set new Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
823 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
824 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
825
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
826 puls cc,b,dp,pc restore IRQ/Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
827
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
828 SetBreak cmpa #SS.Break Tx line break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
829 bne SetSSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
830
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
831 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
832 ldy <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
833 ldd #FCTxBrk*256+TB.Brk [A]=flow control flag, [B]=Tx break enable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
834 orcc #Intmasks disable IRQs while messing with flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
835 ora <FloCtlTx set Tx break flag bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
836 sta <FloCtlTx save Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
837 stb TBReg,y start Tx line break
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
838 bsr BreakSlp go sleep for a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
839 anda #^FCTxBrk clear Tx break flag bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
840 sta <FloCtlTx save Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
841 clr TBReg,y end Tx line break
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
842 puls cc,b,dp,pc restore IRQ/Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
843 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
844
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
845 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
846 ldy <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
847 ldd #FCTxBrk*256+TIRB.Brk [A]=flow control flag, [B]=Tx break enable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
848 orcc #Intmasks disable IRQs while messing with flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
849 ora <FloCtlTx set Tx break flag bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
850 sta <FloCtlTx save Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
851 orb CmdReg,y set Tx line break bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
852 stb CmdReg,y start Tx line break
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
853 bsr BreakSlp go sleep for a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
854 anda #^FCTxBrk clear Tx break flag bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
855 sta <FloCtlTx save Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
856 bra BreakClr go restore RTS output to previous...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
857 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
858 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
859
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
860 SetSSig cmpa #SS.SSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
861 bne SetRelea
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
862 lda PD.CPR,y current process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
863 ldb R$X+1,x LSB of [X] is signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
864 orcc #IntMasks disable IRQs while checking Rx data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
865 ldx <RxDatLen
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
866 bne RSendSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
867 std <SSigPID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
868 puls cc,b,dp,pc restore IRQ/Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
869 RSendSig puls cc restore IRQ/Carry status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
870 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
871 puls a,dp,pc restore dummy A, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
872
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
873 SetRelea cmpa #SS.Relea
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
874 bne SetCDSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
875 leax SSigPID,u point to Rx data signal process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
876 bsr ReleaSig go release signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
877 puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
878
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
879 SetCDSig cmpa #SS.CDSig set DCD signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
880 bne SetCDRel
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
881 lda PD.CPR,y current process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
882 ldb R$X+1,x LSB of [X] is signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
883 std <CDSigPID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
884 puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
885
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
886 SetCDRel cmpa #SS.CDRel release DCD signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
887 bne SetComSt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
888 CDRelSig leax CDSigPID,u point to DCD signal process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
889 bsr ReleaSig go release signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
890 puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
891
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
892 SetComSt cmpa #SS.ComSt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
893 bne SetOpen
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
894 ldd R$Y,x caller's [Y] contains ACIAPAK format type/baud info
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
895 bsr SetPort go save it and set up control/format registers
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
896 ReturnOK puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
897
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
898 SetOpen cmpa #SS.Open
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
899 bne SetClose
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
900 lda R$Y+1,x get LSB of caller's [Y]
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
901 deca real SS.Open from SCF? (SCF sets LSB of [Y] = 1)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
902 bne ReturnOK no, go do nothing but return OK...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
903
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
904 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
905 lda #^(F.DTR!F.RTS) clear (enable) DTR and RTS bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
906 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
907
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
908 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
909 lda #TIRB.RTS enabled DTR and RTS outputs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
910 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
911 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
912
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
913 orcc #IntMasks disable IRQs while setting Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
914 lbra FRegClr go enable DTR and RTS (if not disabled due to Rx flow control)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
915
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
916 SetClose cmpa #SS.Close
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
917 lbne UnSvcErr no, go report error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
918 lda R$Y+1,x real SS.Close from SCF? (SCF sets LSB of [Y] = 0)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
919 bne ReturnOK no, go do nothing but return OK...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
920 leax SSigPID,u point to Rx data signal process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
921 bsr ReleaSig go release signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
922 bra CDRelSig go release DCD signal, return from there...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
923
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
924 ReleaSig pshs cc save IRQ enable status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
925 orcc #IntMasks disable IRQs while releasing signal
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
926 lda PD.CPR,y get current process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
927 suba ,x same as signal process ID?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
928 bne NoReleas no, go return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
929 sta ,x clear this signal's process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
930 NoReleas puls cc,pc restore IRQ enable status, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
931
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
932 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
933 SetPort pshs cc save IRQ enable and Carry status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
934 orcc #IntMasks disable IRQs while setting up DACIA registers
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
935 std <Wrk.Type save type/baud in data area
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
936 lsra *shift parity bits into
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
937 lsra *position for 65C52's
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
938 lsra *format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
939 anda #F.Par clear all except parity bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
940 pshs a save parity temporarily
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
941 comb translate word length bits to 65C52's word length code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
942 andb #F.DatBit clear all except word length bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
943 orb ,s+ mask in parity and clean up stack
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
944 lda <Wrk.Baud get baud information
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
945 anda #BaudRate clear all but baud rate bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
946 leax BaudTabl,pcr
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
947 lda a,x get baud rate setting
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
948 pshs a save it temporarily
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
949 lda <Wrk.Baud get stop bit(s) information
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
950 lsra *shift stop bit into position
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
951 lsra *for 65C52's control register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
952 anda #C.StpBit clear all except stop bit code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
953 ora ,s+ mask in baud rate and clean up stack
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
954 pshs d save stopbits/baudrate and wordlength/parity temporarily
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
955 ldd <Cpy.CR get old control/format register copies
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
956 anda #^(C.StpBit!C.Baud) clear stop bit and baud rate code bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
957 ora ,s+ mask in stop bit(s) and baud rate
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
958 andb #^(F.DatBit!F.Par) clear word length and parity code bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
959 orb ,s+ mask in word length and parity
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
960 ldx <V.PORT get port address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
961 std <Cpy.CR save control/format register copies
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
962 sta CFReg,x set control register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
963 stb CFReg,x set format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
964 puls cc,pc recover IRQ enable and Carry status, return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
965 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
966
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
967 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
968 SetPort pshs cc save IRQ enable and Carry status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
969 orcc #IntMasks disable IRQs while setting up ACIA registers
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
970 std <Wrk.Type save type/baud in data area
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
971 leax BaudTabl,pcr
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
972 andb #BaudRate clear all but baud rate bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
973 ldb b,x get baud rate setting
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
974 pshs b save it temporarily
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
975 ldb <Wrk.Baud get baud info again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
976 andb #^(Ctl.RxCS!Ctl.Baud) clear clock source + baud rate code bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
977 orb ,s+ mask in clock source + baud rate and clean up stack
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
978 ldx <V.PORT get port address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
979 anda #Cmd.Par clear all except parity bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
980 pshs a save new command register contents temporarily
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
981 lda CmdReg,x get current command register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
982 anda #^Cmd.Par clear parity control bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
983 ora ,s+ mask in new parity
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
984 std CmdReg,x set command+control registers
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
985 puls cc,pc recover IRQ enable and Carry status, return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
986 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
987 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
988
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
989 SetDP pshs u save our data pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
990 puls dp set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
991 leas 1,s clean up stack
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
992 rts
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
993
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
994 AccumErr ora <V.ERR
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
995 sta <V.ERR
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
996 rts
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
997
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
998
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
999 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1000 IRQSvc equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1001 pshs dp save system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1002 bsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1003 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1004 ldb CSReg,x get current Control/Status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1005 std <Cpy.ISR save ISR (from D.Poll check) and CSR copies
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1006 bita #ISE.FOB!ISE.Par FRM/OVR/BRK or Parity error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1007 beq ChkRDRF no, go check Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1008 tst DataReg,x read Rx data register to clear DACIA error flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1009 bitb #CS.Break Rx line break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1010 beq ChkParty no, go check if parity error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1011 lda <V.QUIT default to keyboard quit ("Break") code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1012 bra RxBreak go pretend we've received V.QUIT character...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1013
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1014 ChkParty anda #ISE.Par parity error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1015 beq ChkFrame no, go check framing error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1016 lda #ParityEr mark parity error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1017 ChkFrame bitb #CS.Frame framing error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1018 beq ChkOvRun no, go check overrun error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1019 ora #FrmingEr mark Framing error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1020 ChkOvRun tsta any other error flag(s) set?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1021 bne SaveErrs yes, go save them...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1022 ora #OvrFloEr must be overrun error, mark it
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1023 SaveErrs bsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1024 lbra ChkTrDCD go check if DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1025
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1026 ChkRDRF bita #ISE.RxF Rx data?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1027 lbeq ChkTrDCD no, go check DCD transition
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1028 lda DataReg,x get Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1029 RxBreak beq SavRxDat its a null, go save it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1030 clr <SigSent clear signal sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1031 cmpa <V.INTR interrupt?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1032 bne Chk.Quit no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1033 ldb #S$Intrpt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1034 bra SendSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1035 Chk.Quit cmpa <V.QUIT abort?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1036 bne Chk.PChr no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1037 ldb #S$Abort
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1038 SendSig pshs a save Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1039 lda <V.LPRC get last process' ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1040 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1041 puls a recover Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1042 stb <SigSent set signal sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1043 bra SavRxDat go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1044 Chk.PChr cmpa <V.PCHR pause?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1045 bne Chk.Flow no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1046 ldx <V.DEV2 attached device defined?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1047 beq SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1048 sta V.PAUS,x yes, pause attached device
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1049 bra SavRxDat go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1050 Chk.Flow ldb <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1051 bitb #TxSwFlow Tx data software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1052 beq SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1053 cmpa <V.XON XON?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1054 bne Chk.XOff no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1055 ldb #^FCTxXOff clear XOFF received bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1056 andb <FloCtlTx clear software Tx flow control flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1057 bra SetTxFlo go save new Tx flow control flags...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1058 Chk.XOff cmpa <V.XOFF XOFF?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1059 bne SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1060 ldb #FCTxXOff set XOFF received bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1061 orb <FloCtlTx set software Tx flow control flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1062 SetTxFlo stb <FloCtlTx save new Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1063 lbra ChkTrDCD go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1064 SavRxDat ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1065 andb #^FCRxSend clear possible pending XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1066 stb <FloCtlRx save Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1067 ldy <RxBufPut get Rx buffer input pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1068 ldx <RxDatLen Rx get Rx buffer data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1069 cmpx <RxBufSiz Rx buffer already full?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1070 blo NotOvFlo no, go skip overflow error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1071 lda #OvrFloEr mark Rx buffer overflow
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1072 lbsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1073 bra DisRxFlo go ensure Rx is disabled (if possible)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1074 NotOvFlo sta ,y+ save Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1075 cmpy <RxBufEnd end of Rx buffer?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1076 blo SetLayDn no, go keep laydown pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1077 ldy <RxBufPtr get Rx buffer start address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1078 SetLayDn sty <RxBufPut set new Rx data laydown pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1079 leax 1,x one more byte in Rx buffer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1080 stx <RxDatLen save new Rx data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1081 cmpx <RxBufMax at or past maximum (XOFF) fill point?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1082 blo SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1083 DisRxFlo lda <Wrk.XTyp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1084 ldb <Cpy.FR get Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1085 bita #ForceDTR forced DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1086 bne DisRxRTS yes, go check RTS disable...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1087 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1088 bita #DSRFlow DSR/DTR flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1089 beq DisRxRTS no, go check RTS disable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1090 lda <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1091 ora #FCRxDTR mark Rx disabled by DTR
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1092 sta <FloCtlRx save new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1093 orb #F.DTR set (disable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1094 DisRxRTS lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1095 bita #RTSFlow CTS/RTS flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1096 beq NewRxFlo no, go set new Rx flow control...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1097 lda <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1098 ora #FCRxRTS mark Rx disabled by RTS
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1099 sta <FloCtlRx save new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1100 orb #F.RTS set (disable) RTS bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1101 NewRxFlo ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1102 stb <Cpy.FR save Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1103 stb CFReg,x set/clear DTR and RTS in Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1104 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1105 bita #RxSwFlow Rx data software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1106 beq SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1107 lda <V.XOFF XOFF character defined?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1108 beq SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1109 ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1110 bitb #FCRxSent XOFF already sent?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1111 bne SgnlRxD yes, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1112 orb #FCRxSend set send XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1113 stb <FloCtlRx set new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1114 ldb <Cpy.CSR get Control status register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1115 bitb #CS.TxE Tx data register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1116 beq SgnlRxD no, go skip XOFF this time...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1117 sta DataReg,x write XOFF character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1118 ldb #FCRxSent set XOFF sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1119 orb <FloCtlRx mask in current Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1120 andb #^FCRxSend clear send XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1121 stb <FloCtlRx save new flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1122 SgnlRxD ldb <SigSent already sent abort/interrupt signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1123 bne ChkTrDCD yes, go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1124 lda <SSigPID Rx data signal process ID?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1125 beq ChkTrDCD none, go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1126 ldb <SSigSig Rx data signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1127 clr <SSigPID clear Rx data signal
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1128 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1129
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1130 ChkTrDCD ldd <Cpy.ISR get IRQ and Control Status copies
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1131 bita #ISE.DCD DCD transition?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1132 beq CkSuspnd no, go check for suspended process...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1133 bitb #CS.DCD DCD disabled now?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1134 beq SgnlDCD no, go check DCD signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1135 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1136 bita #MdmKill modem kill enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1137 beq SgnlDCD no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1138 ldx <V.PDLHd path descriptor list header
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1139 beq StCDLost no list, go set DCD lost error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1140 lda #PST.DCD DCD lost flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1141 PDListLp sta PD.PST,x set path status flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1142 ldx PD.PLP,x get next path descriptor in list
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1143 bne PDListLp not end of list, go do another...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1144 StCDLost lda #DCDLstEr DCD lost error flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1145 lbsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1146 SgnlDCD lda <CDSigPID get process ID, send a DCD signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1147 beq CkSuspnd no, go check for suspended process...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1148 ldb <CDSigSig get DCD signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1149 clr <CDSigPID clear DCD signal
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1150 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1151
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1152 CkSuspnd clrb clear Carry (for exit) and LSB of process descriptor address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1153 lda <V.WAKE anybody waiting? ([D]=process descriptor address)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1154 beq IRQExit no, go return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1155 stb <V.WAKE mark I/O done
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1156 tfr d,x copy process descriptor pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1157 lda P$State,x get state flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1158 anda #^Suspend clear suspend state
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1159 sta P$State,x save state flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1160 IRQExit puls dp,pc recover system DP, return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1161 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1162
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1163 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1164 IRQSvc equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1165 pshs dp save system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1166 bsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1167 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1168 ldb StatReg,x get current Status register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1169 stb <Cpy.Stat save Status register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1170 bitb #Stat.Err error(s)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1171 beq ChkRDRF no, go check Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1172 tst DataReg,x read Rx data register to clear ACIA error flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1173 bitb #Stat.Frm framing error (assume Rx line Break)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1174 beq ChkParty no, go check if parity error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1175 lda <V.QUIT default to keyboard quit ("Break") code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1176 bra RxBreak go pretend we've received V.QUIT character...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1177
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1178 ChkParty clra clear old IRQ status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1179 bitb #Stat.Par parity error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1180 beq ChkOvRun no, go check overrun error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1181 ora #ParityEr mark parity error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1182 ChkOvRun bita #Stat.Ovr overrun error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1183 beq SaveErrs no, go save errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1184 ora #OvrFloEr mark overrun error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1185 SaveErrs bsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1186 lbra ChkTrDCD go check if DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1187
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1188 ChkRDRF bitb #Stat.RxF Rx data?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1189 lbeq ChkTrDCD no, go check DCD transition
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1190 lda DataReg,x get Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1191 RxBreak beq SavRxDat its a null, go save it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1192 clr <SigSent clear signal sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1193 cmpa <V.INTR interrupt?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1194 bne Chk.Quit no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1195 ldb #S$Intrpt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1196 bra SendSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1197 Chk.Quit cmpa <V.QUIT abort?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1198 bne Chk.PChr no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1199 ldb #S$Abort
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1200 SendSig pshs a save Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1201 lda <V.LPRC get last process' ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1202 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1203 puls a recover Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1204 stb <SigSent set signal sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1205 bra SavRxDat go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1206 Chk.PChr cmpa <V.PCHR pause?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1207 bne Chk.Flow no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1208 ldx <V.DEV2 attached device defined?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1209 beq SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1210 sta V.PAUS,x yes, pause attached device
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1211 bra SavRxDat go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1212 Chk.Flow ldb <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1213 bitb #TxSwFlow Tx data software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1214 beq SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1215 cmpa <V.XON XON?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1216 bne Chk.XOff no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1217 ldb #^FCTxXOff clear XOFF received bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1218 andb <FloCtlTx clear software Tx flow control flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1219 bra SetTxFlo go save new Tx flow control flags...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1220 Chk.XOff cmpa <V.XOFF XOFF?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1221 bne SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1222 ldb #FCTxXOff set XOFF received bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1223 orb <FloCtlTx set software Tx flow control flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1224 SetTxFlo stb <FloCtlTx save new Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1225 lbra ChkTrDCD go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1226 SavRxDat ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1227 andb #^FCRxSend clear possible pending XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1228 stb <FloCtlRx save Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1229 ldy <RxBufPut get Rx buffer input pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1230 ldx <RxDatLen Rx get Rx buffer data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1231 cmpx <RxBufSiz Rx buffer already full?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1232 blo NotOvFlo no, go skip overflow error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1233 lda #OvrFloEr mark Rx buffer overflow
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1234 lbsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1235 bra DisRxFlo go ensure Rx is disabled (if possible)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1236 NotOvFlo sta ,y+ save Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1237 cmpy <RxBufEnd end of Rx buffer?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1238 blo SetLayDn no, go keep laydown pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1239 ldy <RxBufPtr get Rx buffer start address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1240 SetLayDn sty <RxBufPut set new Rx data laydown pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1241 leax 1,x one more byte in Rx buffer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1242 stx <RxDatLen save new Rx data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1243 cmpx <RxBufMax at or past maximum fill point?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1244 blo SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1245 DisRxFlo ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1246 lda <Wrk.XTyp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1247 ldb CmdReg,x get current Command register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1248 bita #ForceDTR forced DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1249 bne DisRxRTS yes, go check RTS disable...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1250 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1251 bita #DSRFlow DSR/DTR flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1252 beq DisRxRTS no, go check RTS disable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1253 lda <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1254 ora #FCRxDTR mark Rx disabled by DTR
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1255 sta <FloCtlRx save new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1256 andb #^Cmd.DTR clear (disable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1257 DisRxRTS lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1258 bita #RTSFlow CTS/RTS flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1259 beq NewRxFlo no, go set new Rx flow control...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1260 lda <FloCtlTx get Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1261 bita #FCTxBrk currently transmitting line Break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1262 bne NewRxFlo yes, go set new Rx flow control...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1263 lda <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1264 ora #FCRxRTS mark Rx disabled by RTS
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1265 sta <FloCtlRx save new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1266 andb #^Cmd.TIRB clear Tx IRQ/RTS/Break control bits (disable RTS)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1267 NewRxFlo stb CmdReg,x set/clear DTR and RTS in Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1268 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1269 bita #RxSwFlow Rx software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1270 beq SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1271 lda <V.XOFF XOFF character defined?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1272 beq SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1273 ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1274 bitb #FCRxSent XOFF already sent?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1275 bne SgnlRxD yes, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1276 orb #FCRxSend set send XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1277 stb <FloCtlRx set new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1278 ldb StatReg,x get new Status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1279 bitb #Stat.TxE Tx data register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1280 beq SgnlRxD no, go skip XOFF this time...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1281 sta DataReg,x write XOFF character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1282 ldb #FCRxSent set XOFF sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1283 orb <FloCtlRx mask in current Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1284 andb #^FCRxSend clear send XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1285 stb <FloCtlRx save new flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1286 SgnlRxD ldb <SigSent already sent abort/interrupt signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1287 bne ChkTrDCD yes, go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1288 lda <SSigPID Rx data signal process ID?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1289 beq ChkTrDCD none, go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1290 ldb <SSigSig Rx data signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1291 clr <SSigPID clear Rx data signal
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1292 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1293
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1294 ChkTrDCD ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1295 lda <Cpy.Stat get Status register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1296 tfr a,b copy it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1297 eora <CpyDCDSR mark changes from old DSR+DCD status copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1298 andb #Stat.DSR!Stat.DCD clear all but DSR+DCD status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1299 stb <CpyDCDSR save new DSR+DCD status copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1300 bita <Mask.DCD DCD transition?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1301 beq CkSuspnd no, go check for suspended process...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1302 bitb <Mask.DCD DCD disabled now?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1303 beq SgnlDCD no, go check DCD signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1304 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1305 bita #MdmKill modem kill enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1306 beq SgnlDCD no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1307 ldx <V.PDLHd path descriptor list header
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1308 beq StCDLost no list, go set DCD lost error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1309 lda #PST.DCD DCD lost flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1310 PDListLp sta PD.PST,x set path status flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1311 ldx PD.PLP,x get next path descriptor in list
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1312 bne PDListLp not end of list, go do another...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1313 StCDLost lda #DCDLstEr DCD lost error flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1314 lbsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1315 SgnlDCD lda <CDSigPID get process ID, send a DCD signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1316 beq CkSuspnd no, go check for suspended process...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1317 ldb <CDSigSig get DCD signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1318 clr <CDSigPID clear DCD signal
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1319 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1320
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1321 CkSuspnd clrb clear Carry (for exit) and LSB of process descriptor address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1322 lda <V.WAKE anybody waiting? ([D]=process descriptor address)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1323 beq IRQExit no, go return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1324 stb <V.WAKE mark I/O done
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1325 tfr d,x copy process descriptor pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1326 lda P$State,x get state flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1327 anda #^Suspend clear suspend state
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1328 sta P$State,x save state flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1329 IRQExit puls dp,pc recover system DP, return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1330 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1331 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1332
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1333
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1334 emod
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1335 ModSize equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1336 end
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1337