annotate level2/modules/xacia.asm @ 899:6841c75afc62

Modified
author boisy
date Fri, 17 Jan 2003 21:04:02 +0000
parents b3bfa479f8d0
children bdd2f61d5dbc
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1 ********************************************************************
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2 * XACIA - Enhanced 6551 driver
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3 *
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4 * $Id$
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5 *
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6 * Ed. Comments Who YY/MM/DD
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7 * ------------------------------------------------------------------
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8 * 10 Bruce Isted distribution version BRI
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9
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10 nam XACIA
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11 ttl Enhanced 6551 driver
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12
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13 ifp1
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14 use defsfile
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15 endc
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16
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17 * miscellaneous definitions
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18 DCDStBit equ %00100000 DCD status bit for SS.CDSta call
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19 DSRStBit equ %01000000 DSR status bit for SS.CDSta call
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20 Edtn equ 10
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21 Vrsn equ 1
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22
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23 * conditional assembly flags
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24 *A6551 set true 6551 SACIA version
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25 *A6552 set false 65C52 DACIA version
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26 SlpBreak set TkPerSec/2+1 line Break duration
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27 SlpHngUp set TkPerSec/4+1 hang up (drop DTR) duration
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28
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29 ifeq A6552-true
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30 nam DACIA
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31 ttl 65C52 Dual ACIA driver
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32 else
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33
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34 ifeq A6551-true
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35 nam SACIA
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36 ttl 6551 Single ACIA driver
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37 endc
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38 endc
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39
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40 ifeq A6552-true
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41 * 65C52 register definitions
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42 org 0
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43 ISReg rmb 1 IRQ Status (read only)
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44 IEReg equ ISReg IRQ Enable (write only)
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45 CSReg rmb 1 Control Status (read only)
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46 CFReg equ CSReg Control/Format (write only)
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47 CDReg rmb 1 Compare Data (write only, unused in this driver)
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48 TBReg equ CDReg Transmit Break (write only)
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49 DataReg rmb 1 receive/transmit Data (read Rx / write Tx)
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50
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51 * IRQ Status/Enable bit definitions
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52 ISE.IRQ equ %10000000 IRQ occurred/enable
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53 ISE.TxE equ %01000000 Tx data register Empty
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54 ISE.CTS equ %00100000 CTS transition
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55 ISE.DCD equ %00010000 DCD transition
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56 ISE.DSR equ %00001000 DSR transition
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57 ISE.FOB equ %00000100 Rx data Framing or Overrun error, or Break
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58 ISE.Par equ %00000010 Rx data Parity error
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59 ISE.RxF equ %00000001 Rx data register Full
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60
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61 ISE.Errs equ ISE.FOB!ISE.Par IRQ Status error bits
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62 ISE.Flip equ $00 all ISR bits active when set
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63 ISE.Mask equ ISE.CTS!ISE.DCD!ISE.DSR!ISE.FOB!ISE.Par!ISE.RxF active IRQs
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64
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65 * Control Status bit definitions
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66 CS.Frame equ %10000000 framing error (set=error)
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67 CS.TxE equ %01000000 Tx data empty (set=empty)
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68 CS.CTS equ %00100000 CTS input (set=disabled)
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69 CS.DCD equ %00010000 DCD input (set=disabled)
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70 CS.DSR equ %00001000 DSR input (set=disabled)
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71 CS.Break equ %00000100 Rx line break (set=received break)
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72 CS.DTR equ %00000010 DTR output (set=disabled)
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73 CS.RTS equ %00000001 RTS output (set=disabled)
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74
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75 * Control bit definitions
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76 C.TBRCDR equ %01000000 Tx Break/Compare Data register access (set=Tx Break)
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77 C.StpBit equ %00100000 stop bits (set=two, clear=one)
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78 C.Echo equ %00010000 local echo (set=activated)
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79 C.Baud equ %00001111 see baud rate table below
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80
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81 * baud rate table
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82 org 0
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83 BR.00050 rmb 1 50 baud (not supported)
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84 BR.00110 rmb 1 109.92 baud
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85 BR.00135 rmb 1 134.58 baud (not supported)
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86 BR.00150 rmb 1 150 baud (not supported)
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87 BR.00300 rmb 1 300 baud
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88 BR.00600 rmb 1 600 baud
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89 BR.01200 rmb 1 1200 baud
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90 BR.01800 rmb 1 1800 baud (not supported)
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91 BR.02400 rmb 1 2400 baud
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92 BR.03600 rmb 1 3600 baud (not supported)
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93 BR.04800 rmb 1 4800 baud
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94 BR.07200 rmb 1 7200 baud (not supported)
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95 BR.09600 rmb 1 9600 baud
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96 BR.19200 rmb 1 19200 baud
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97 BR.38400 rmb 1 38400 baud
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98 BR.ExClk rmb 1 external Rx and Tx clocks (not supported)
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99
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100 * Format bit definitions
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101 F.Slct equ %10000000 register select (set=Format, clear=Control)
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102 F.DatBit equ %01100000 see data bit table below
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103 F.Par equ %00011100 see parity table below
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104 F.DTR equ %00000010 DTR output (set=disabled)
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105 F.RTS equ %00000001 RTS output (set=disabled)
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106
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107 * data bit table
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108 DB.5 equ %00000000 five data bits per character
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109 DB.6 equ %00100000 six data bits per character
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110 DB.7 equ %01000000 seven data bits per character
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111 DB.8 equ %01100000 eight data bits per character
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112
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113 * parity table
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114 Par.None equ %00000000
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115 Par.Odd equ %00000100
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116 Par.Even equ %00001100
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117 Par.Mark equ %00010100
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118 Par.Spac equ %00011100
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119
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120 * Transmit Break bit definitions
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121 TB.Brk equ %00000010 Tx break control (set=transmit continuous line Break)
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122 TB.Par equ %00000001 parity check (set=parity bit to ISE.Par, clear=normal)
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123 else
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124
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125 ifeq A6551-true
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126 * 6551 register definitions
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127 org 0
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128 DataReg rmb 1 receive/transmit Data (read Rx / write Tx)
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129 StatReg rmb 1 status (read only)
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130 PRstReg equ StatReg programmed reset (write only)
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131 CmdReg rmb 1 command (read/write)
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132 CtlReg rmb 1 control (read/write)
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133
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134 * Status bit definitions
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135 Stat.IRQ equ %10000000 IRQ occurred
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136 Stat.DSR equ %01000000 DSR level (clear = active)
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137 Stat.DCD equ %00100000 DCD level (clear = active)
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138 Stat.TxE equ %00010000 Tx data register Empty
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139 Stat.RxF equ %00001000 Rx data register Full
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140 Stat.Ovr equ %00000100 Rx data Overrun error
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141 Stat.Frm equ %00000010 Rx data Framing error
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142 Stat.Par equ %00000001 Rx data Parity error
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143
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144 Stat.Err equ Stat.Ovr!Stat.Frm!Stat.Par Status error bits
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145 Stat.Flp equ $00 all Status bits active when set
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146 Stat.Msk equ Stat.IRQ!Stat.RxF active IRQs
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147
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148 * Control bit definitions
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149 Ctl.Stop equ %10000000 stop bits (set=two, clear=one)
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150 Ctl.DBit equ %01100000 see data bit table below
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151 Ctl.RxCS equ %00010000 Rx clock source (set=baud rate, clear=external)
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152 Ctl.Baud equ %00001111 see baud rate table below
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153
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154 * data bit table
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155 DB.8 equ %00000000 eight data bits per character
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156 DB.7 equ %00100000 seven data bits per character
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157 DB.6 equ %01000000 six data bits per character
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158 DB.5 equ %01100000 five data bits per character
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159
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160 * baud rate table
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161 org $00
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162 BR.ExClk rmb 1 16x external clock (not supported)
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163 org $11
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164 BR.00050 rmb 1 50 baud (not supported)
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165 BR.00075 rmb 1 75 baud (not supported)
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166 BR.00110 rmb 1 109.92 baud
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167 BR.00135 rmb 1 134.58 baud (not supported)
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168 BR.00150 rmb 1 150 baud (not supported)
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169 BR.00300 rmb 1 300 baud
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170 BR.00600 rmb 1 600 baud
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171 BR.01200 rmb 1 1200 baud
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172 BR.01800 rmb 1 1800 baud (not supported)
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173 BR.02400 rmb 1 2400 baud
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174 BR.03600 rmb 1 3600 baud (not supported)
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175 BR.04800 rmb 1 4800 baud
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176 BR.07200 rmb 1 7200 baud (not supported)
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177 BR.09600 rmb 1 9600 baud
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178 BR.19200 rmb 1 19200 baud
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179
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180 * Command bit definitions
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181 Cmd.Par equ %11100000 see parity table below
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182 Cmd.Echo equ %00010000 local echo (set=activated)
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183 Cmd.TIRB equ %00001100 see Tx IRQ/RTS/Break table below
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184 Cmd.RxI equ %00000010 Rx IRQ (set=disabled)
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185 Cmd.DTR equ %00000001 DTR output (set=enabled)
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186
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187 * parity table
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188 Par.None equ %00000000
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189 Par.Odd equ %00100000
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190 Par.Even equ %01100000
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191 Par.Mark equ %10100000
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192 Par.Spac equ %11100000
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193
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194 * Tx IRQ/RTS/Break table
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195 TIRB.Off equ %00000000 RTS & Tx IRQs disabled
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196 TIRB.On equ %00000100 RTS & Tx IRQs enabled
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197 TIRB.RTS equ %00001000 RTS enabled, Tx IRQs disabled
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198 TIRB.Brk equ %00001100 RTS enabled, Tx IRQs disabled, Tx line Break
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199 endc
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200 endc
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201
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202 * V.ERR bit definitions
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203 DCDLstEr equ %00100000 DCD lost error
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204 OvrFloEr equ %00000100 Rx data overrun or Rx buffer overflow error
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205 FrmingEr equ %00000010 Rx data framing error
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206 ParityEr equ %00000001 Rx data parity error
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207
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208 * FloCtlRx bit definitions
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209 FCRxSend equ %10000000 send flow control character
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210 FCRxSent equ %00010000 Rx disabled due to XOFF sent
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211 FCRxDTR equ %00000010 Rx disabled due to DTR
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212 FCRxRTS equ %00000001 Rx disabled due to RTS
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213
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214 * FloCtlTx bit definitions
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diff changeset
215 FCTxXOff equ %10000000 due to XOFF received
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parents:
diff changeset
216 FCTxBrk equ %00000010 due to currently transmitting Break
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parents:
diff changeset
217
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parents:
diff changeset
218 * Wrk.Type bit definitions
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parents:
diff changeset
219 Parity equ %11100000 parity bits
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parents:
diff changeset
220 MdmKill equ %00010000 modem kill option
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parents:
diff changeset
221 RxSwFlow equ %00001000 Rx data software (XON/XOFF) flow control
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parents:
diff changeset
222 TxSwFlow equ %00000100 Tx data software (XON/XOFF) flow control
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parents:
diff changeset
223 RTSFlow equ %00000010 CTS/RTS hardware flow control
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parents:
diff changeset
224 DSRFlow equ %00000001 DSR/DTR hardware flow control
6641a883d6b0 Initial revision
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parents:
diff changeset
225
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parents:
diff changeset
226 * Wrk.Baud bit definitions
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parents:
diff changeset
227 StopBits equ %10000000 number of stop bits code
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parents:
diff changeset
228 WordLen equ %01100000 word length code
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parents:
diff changeset
229 BaudRate equ %00001111 baud rate code
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parents:
diff changeset
230
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parents:
diff changeset
231 * Wrk.XTyp bit definitions
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parents:
diff changeset
232 SwpDCDSR equ %10000000 swap DCD+DSR bits (valid for 6551 only)
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parents:
diff changeset
233 ForceDTR equ %01000000 don't drop DTR in term routine
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parents:
diff changeset
234 RxBufPag equ %00001111 input buffer page count
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parents:
diff changeset
235
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parents:
diff changeset
236 * static data area definitions
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diff changeset
237 org V.SCF allow for SCF manager data area
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parents:
diff changeset
238
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parents:
diff changeset
239 ifeq A6552-true
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parents:
diff changeset
240 Cpy.CR rmb 1 Control register copy (MUST immediately precede Cpy.FR)
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parents:
diff changeset
241 Cpy.FR rmb 1 Format register copy (MUST immediately follow Cpy.CR)
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parents:
diff changeset
242 Cpy.ISR rmb 1 IRQ Status register copy (MUST immediately precede Cpy.CSR)
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parents:
diff changeset
243 Cpy.CSR rmb 1 Control Status register copy (MUST immediately follow Cpy.ISR)
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parents:
diff changeset
244 else
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parents:
diff changeset
245
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parents:
diff changeset
246 ifeq A6551-true
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parents:
diff changeset
247 Cpy.Stat rmb 1 Status register copy
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parents:
diff changeset
248 CpyDCDSR rmb 1 DSR+DCD status copy
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parents:
diff changeset
249 Mask.DCD rmb 1 DCD status bit mask (MUST immediately precede Mask.DSR)
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parents:
diff changeset
250 Mask.DSR rmb 1 DSR status bit mask (MUST immediately follow Mask.DCD)
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251 endc
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parents:
diff changeset
252 endc
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parents:
diff changeset
253
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parents:
diff changeset
254 CDSigPID rmb 1 process ID for CD signal
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parents:
diff changeset
255 CDSigSig rmb 1 CD signal code
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parents:
diff changeset
256 FloCtlRx rmb 1 Rx flow control flags
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parents:
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257 FloCtlTx rmb 1 Tx flow control flags
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parents:
diff changeset
258 RxBufEnd rmb 2 end of Rx buffer
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parents:
diff changeset
259 RxBufGet rmb 2 Rx buffer output pointer
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parents:
diff changeset
260 RxBufMax rmb 2 Send XOFF (if enabled) at this point
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parents:
diff changeset
261 RxBufMin rmb 2 Send XON (if XOFF sent) at this point
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parents:
diff changeset
262 RxBufPtr rmb 2 pointer to Rx buffer
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parents:
diff changeset
263 RxBufPut rmb 2 Rx buffer input pointer
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parents:
diff changeset
264 RxBufSiz rmb 2 Rx buffer size
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parents:
diff changeset
265 RxDatLen rmb 2 current length of data in Rx buffer
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parents:
diff changeset
266 SigSent rmb 1 keyboard abort/interrupt signal already sent
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parents:
diff changeset
267 SSigPID rmb 1 SS.SSig process ID
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parents:
diff changeset
268 SSigSig rmb 1 SS.SSig signal code
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parents:
diff changeset
269 WritFlag rmb 1 initial write attempt flag
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parents:
diff changeset
270 Wrk.Type rmb 1 type work byte (MUST immediately precede Wrk.Baud)
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parents:
diff changeset
271 Wrk.Baud rmb 1 baud work byte (MUST immediately follow Wrk.Type)
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parents:
diff changeset
272 Wrk.XTyp rmb 1 extended type work byte
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diff changeset
273 RxBufDSz equ 256-. default Rx buffer gets remainder of page...
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parents:
diff changeset
274 RxBuff rmb RxBufDSz default Rx buffer
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parents:
diff changeset
275 MemSize equ .
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parents:
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276
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parents:
diff changeset
277 mod ModSize,ModName,Drivr+Objct,ReEnt+Vrsn,ModEntry,MemSize
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parents:
diff changeset
278
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parents:
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279 fcb UPDAT. access mode(s)
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parents:
diff changeset
280
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parents:
diff changeset
281 ifeq A6552-true
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parents:
diff changeset
282 ModName fcs "DACIA"
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parents:
diff changeset
283 else
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parents:
diff changeset
284
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parents:
diff changeset
285 ifeq A6551-true
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parents:
diff changeset
286 ModName fcs "SACIA"
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parents:
diff changeset
287 endc
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parents:
diff changeset
288 endc
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parents:
diff changeset
289
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parents:
diff changeset
290 fcb Edtn
6641a883d6b0 Initial revision
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parents:
diff changeset
291
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parents:
diff changeset
292 SlotSlct fcb MPI.Slot selected MPI slot
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parents:
diff changeset
293
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parents:
diff changeset
294 ModEntry equ *
6641a883d6b0 Initial revision
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parents:
diff changeset
295 lbra Init
6641a883d6b0 Initial revision
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parents:
diff changeset
296 lbra Read
6641a883d6b0 Initial revision
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parents:
diff changeset
297 lbra Writ
6641a883d6b0 Initial revision
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parents:
diff changeset
298 lbra GStt
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parents:
diff changeset
299 lbra SStt
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parents:
diff changeset
300 lbra Term
6641a883d6b0 Initial revision
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parents:
diff changeset
301
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parents:
diff changeset
302 IRQPckt equ *
6641a883d6b0 Initial revision
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parents:
diff changeset
303
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parents:
diff changeset
304 ifeq A6552-true
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parents:
diff changeset
305 Pkt.Flip fcb ISE.Flip D.Poll flip byte
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parents:
diff changeset
306 Pkt.Mask fcb ISE.Mask D.Poll mask byte
6641a883d6b0 Initial revision
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parents:
diff changeset
307 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
308
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parents:
diff changeset
309 ifeq A6551-true
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parents:
diff changeset
310 Pkt.Flip fcb Stat.Flp flip byte
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parents:
diff changeset
311 Pkt.Mask fcb Stat.Msk mask byte
6641a883d6b0 Initial revision
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parents:
diff changeset
312 endc
6641a883d6b0 Initial revision
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parents:
diff changeset
313 endc
6641a883d6b0 Initial revision
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parents:
diff changeset
314
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parents:
diff changeset
315 fcb $0A priority
6641a883d6b0 Initial revision
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parents:
diff changeset
316
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parents:
diff changeset
317 BaudTabl equ *
6641a883d6b0 Initial revision
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parents:
diff changeset
318
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parents:
diff changeset
319 ifeq A6552-true
6641a883d6b0 Initial revision
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parents:
diff changeset
320 fcb BR.00110,BR.00300,BR.00600
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parents:
diff changeset
321 fcb BR.01200,BR.02400,BR.04800
6641a883d6b0 Initial revision
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parents:
diff changeset
322 fcb BR.09600,BR.19200,BR.38400
6641a883d6b0 Initial revision
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parents:
diff changeset
323 else
6641a883d6b0 Initial revision
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parents:
diff changeset
324
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parents:
diff changeset
325 ifeq A6551-true
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parents:
diff changeset
326 fcb BR.00110,BR.00300,BR.00600
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parents:
diff changeset
327 fcb BR.01200,BR.02400,BR.04800
6641a883d6b0 Initial revision
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parents:
diff changeset
328 fcb BR.09600,BR.19200
6641a883d6b0 Initial revision
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parents:
diff changeset
329 endc
6641a883d6b0 Initial revision
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parents:
diff changeset
330 endc
6641a883d6b0 Initial revision
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parents:
diff changeset
331
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parents:
diff changeset
332
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parents:
diff changeset
333 * NOTE: SCFMan has already cleared all device memory except for V.PAGE and
6641a883d6b0 Initial revision
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parents:
diff changeset
334 * V.PORT. Zero-default variables are: CDSigPID, CDSigSig, Wrk.XTyp.
6641a883d6b0 Initial revision
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parents:
diff changeset
335 Init equ *
6641a883d6b0 Initial revision
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parents:
diff changeset
336 clrb default to no error...
6641a883d6b0 Initial revision
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parents:
diff changeset
337 pshs cc,b,dp save IRQ/Carry status, dummy B, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
338 lbsr SetDP go set our DP
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parents:
diff changeset
339 pshs y save descriptor pointer
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diff changeset
340 ldd <V.PORT base hardware address
6641a883d6b0 Initial revision
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parents:
diff changeset
341
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parents:
diff changeset
342 ifeq A6552-true
6641a883d6b0 Initial revision
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parents:
diff changeset
343 else
6641a883d6b0 Initial revision
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parents:
diff changeset
344
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parents:
diff changeset
345 ifeq A6551-true
6641a883d6b0 Initial revision
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parents:
diff changeset
346 addd #1 point to 6551 status address
6641a883d6b0 Initial revision
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parents:
diff changeset
347 endc
6641a883d6b0 Initial revision
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parents:
diff changeset
348 endc
6641a883d6b0 Initial revision
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parents:
diff changeset
349
6641a883d6b0 Initial revision
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parents:
diff changeset
350 leax IRQPckt,pcr
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
351 leay IRQSvc,pcr
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
352 os9 F$IRQ
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
353 puls y recover descriptor pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
354 lbcs ErrExit go report error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
355 ldb M$Opt,y get option size
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
356 cmpb #IT.XTYP-IT.DTP room for extended type byte?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
357 bls DfltInfo no, go use defaults...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
358
6641a883d6b0 Initial revision
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parents:
diff changeset
359 ifeq A6552-true
6641a883d6b0 Initial revision
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parents:
diff changeset
360 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
361
6641a883d6b0 Initial revision
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parents:
diff changeset
362 ifeq A6551-true
6641a883d6b0 Initial revision
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parents:
diff changeset
363 ldd #Stat.DCD*256+Stat.DSR default (unswapped) DCD+DSR masks
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
364 tst IT.XTYP,y check extended type byte for swapped DCD & DSR bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
365 bpl NoSwap no, go skip swapping them...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
366 exg a,b swap to DSR+DCD masks
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
367 NoSwap std <Mask.DCD save DCD+DSR (or DSR+DCD) masks
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
368 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
369 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
370
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
371 lda IT.XTYP,y get extended type byte
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
372 sta <Wrk.XTyp save it
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
373 anda #RxBufPag clear all but Rx buffer page count bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
374 beq DfltInfo none, go use defaults...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
375 clrb make data size an even number of pages
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
376 pshs u save data pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
377 os9 F$SRqMem get extended buffer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
378 tfr u,x copy address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
379 puls u recover data pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
380 lbcs TermExit error, go remove IRQ entry and exit...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
381 bra SetRxBuf
6641a883d6b0 Initial revision
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parents:
diff changeset
382
6641a883d6b0 Initial revision
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parents:
diff changeset
383 DfltInfo ldd #RxBufDSz default Rx buffer size
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
384 leax RxBuff,u default Rx buffer address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
385 SetRxBuf std <RxBufSiz save Rx buffer size
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
386 stx <RxBufPtr save Rx buffer address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
387 stx <RxBufGet set initial Rx buffer input address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
388 stx <RxBufPut set initial Rx buffer output address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
389 leax d,x point to end of Rx buffer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
390 stx <RxBufEnd save Rx buffer end address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
391 subd #80 characters available in Rx buffer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
392 std <RxBufMax set auto-XOFF threshold
6641a883d6b0 Initial revision
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parents:
diff changeset
393 ldd #10 characters remaining in Rx buffer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
394 std <RxBufMin set auto-XON threshold after auto-XOFF
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
395
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
396 ifeq A6552-true
6641a883d6b0 Initial revision
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parents:
diff changeset
397 ldd #C.TBRCDR*256+(F.Slct!F.DTR!F.RTS) [A]=control, [B]=format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
398 sta <Cpy.CR save control register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
399 lda <Wrk.XTyp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
400 anda #ForceDTR forced DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
401 beq NoDTR no, don't enable DTR yet
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
402 andb #^F.DTR clear (enable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
403 NoDTR stb <Cpy.FR save format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
404 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
405
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
406 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
407 ldb #TIRB.RTS default command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
408 lda <Wrk.XTyp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
409 anda #ForceDTR forced DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
410 beq NoDTR no, don't enable DTR yet
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
411 orb #Cmd.DTR set (enable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
412 NoDTR ldx <V.PORT get port address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
413 stb CmdReg,x set new command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
414 endc
6641a883d6b0 Initial revision
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parents:
diff changeset
415 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
416
6641a883d6b0 Initial revision
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parents:
diff changeset
417 ldd IT.PAR,y [A] = IT.PAR, [B] = IT.BAU from descriptor
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
418 lbsr SetPort go save it and set up control/format registers
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
419 orcc #IntMasks disable IRQs while setting up hardware
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
420 lda >PIA1Base+3 get PIA CART* input control register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
421 anda #$FC clear PIA CART* control bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
422 sta >PIA1Base+3 disable PIA CART* FIRQs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
423 lda >PIA1Base+2 clear possible pending PIA CART* FIRQ
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
424 lda #$01 GIME CART* IRQ bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
425 ora >D.IRQER mask in current GIME IRQ enables
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
426 sta >D.IRQER save GIME CART* IRQ enable shadow register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
427 sta >IrqEnR enable GIME CART* IRQs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
428
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
429 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
430 lda #ISE.IRQ!ISE.Mask DACIA IRQ enables
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
431 sta IEReg,x enable DACIA IRQs for this port ([X]=V.PORT from SetPort)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
432 ldb ISReg,x ensure old CTS, DCD, and DSR transition IRQ flags are clear
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
433 ldb DataReg,x ensure old error and Rx data IRQ flags are clear
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
434 ldb ISReg,x ... again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
435 ldb DataReg,x ... and again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
436 ldd ISReg,x get new IRQ and Control status registers
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
437 eora Pkt.Flip,pcr flip bits per D.Poll
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
438 anda Pkt.Mask,pcr any IRQ(s) still pending?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
439 lbne NRdyErr yes, go report error... (device not plugged in?)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
440 std <Cpy.ISR save new IRQ and Control status register copies
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
441 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
442
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
443 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
444 lda StatReg,x ensure old IRQ flags are clear
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
445 lda DataReg,x ensure old error and Rx data IRQ flags are clear
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
446 lda StatReg,x ... again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
447 lda DataReg,x ... and again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
448 lda StatReg,x get new Status register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
449 sta <Cpy.Stat save Status copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
450 tfr a,b copy it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
451 eora Pkt.Flip,pcr flip bits per D.Poll
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
452 anda Pkt.Mask,pcr any IRQ(s) still pending?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
453 lbne NRdyErr yes, go report error... (device not plugged in?)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
454 andb #Stat.DSR!Stat.DCD clear all but DSR+DCD status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
455 stb <CpyDCDSR save new DCD+DSR status copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
456 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
457 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
458
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
459 lda SlotSlct,pcr get MPI slot select value
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
460 bmi NoSelect no MPI slot select, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
461 sta >MPI.Slct set MPI slot select register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
462 NoSelect puls cc,b,dp,pc recover IRQ/Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
463
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
464
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
465 Term equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
466 clrb default to no error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
467 pshs cc,b,dp save IRQ/Carry status, dummy B, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
468 lbsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
469
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
470 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
471 lda #^ISE.IRQ disable all DACIA IRQs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
472 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
473 sta IEReg,x disable DACIA IRQs for this port
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
474 lda <Cpy.FR get format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
475 ora #F.DTR!F.RTS set (disable) DTR and RTS bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
476 ldb <Wrk.XTyp get extended type byte
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
477 andb #ForceDTR forced DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
478 beq KeepDTR no, go leave DTR disabled...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
479 anda #^F.DTR clear (enable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
480 KeepDTR sta CFReg,x set DTR and RTS enable/disable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
481 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
482
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
483 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
484 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
485 lda CmdReg,x get current Command register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
486 anda #^(Cmd.TIRB!Cmd.DTR) disable Tx IRQs, RTS, and DTR
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
487 ora #Cmd.RxI disable Rx IRQs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
488 ldb <Wrk.XTyp get extended type byte
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
489 andb #ForceDTR forced DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
490 beq KeepDTR no, go leave DTR disabled...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
491 ora #Cmd.DTR set (enable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
492 KeepDTR sta CmdReg,x set DTR and RTS enable/disable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
493 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
494 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
495
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
496 ldd <RxBufSiz get Rx buffer size
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
497 tsta less than 256 bytes?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
498 beq TermExit yes, no system memory to return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
499 pshs u save data pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
500 ldu <RxBufPtr get address of system memory
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
501 os9 F$SRtMem
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
502 puls u recover data pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
503 TermExit ldd <V.PORT base hardware address is status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
504
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
505 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
506 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
507
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
508 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
509 addd #1 point to 6551 status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
510 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
511 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
512
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
513 ldx #$0000 remove IRQ table entry
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
514 leay IRQSvc,pcr
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
515 puls cc recover IRQ/Carry status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
516 os9 F$IRQ
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
517 puls a,dp,pc restore dummy A, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
518
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
519
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
520 ReadSlp ldd >D.Proc process descriptor address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
521 sta <V.WAKE save MSB for IRQ service routine
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
522 tfr d,x copy process descriptor address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
523 ldb P$State,x get process state flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
524 orb #Suspend set suspend flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
525 stb P$State,x put process in suspend state
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
526 lbsr Sleep1 go suspend process...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
527 ldx >D.Proc process descriptor address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
528 ldb P$Signal,x pending signal for this process?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
529 beq ChkState no, go check process state...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
530 cmpb #S$Intrpt do we honor signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
531 bls ErrExit yes, go do it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
532 ChkState ldb P$State,x get process state
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
533 bitb #Condem we be dead?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
534 bne PrAbtErr yes, go do it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
535 ldb <V.WAKE true interrupt?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
536 bne ReadSlp no, go suspend again...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
537 ReadLoop puls cc,b,dp recover IRQ/Carry status, dummy B, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
538
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
539 Read equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
540 clrb default to no errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
541 pshs cc,b,dp save IRQ/Carry status, dummy B, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
542 lbsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
543 orcc #IntMasks disable IRQs while checking Rx flow control
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
544 lda <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
545 beq ReadChar none, go get Rx character...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
546 ldx <RxDatLen get Rx data count again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
547 cmpx <RxBufMin at or below XON level?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
548 bhi ReadChar no, go get Rx character...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
549 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
550 bita #FCRxSent Rx disabled due to XOFF sent?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
551 beq ChkHWHS no, go check hardware handshake(s)...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
552 ldb <FloCtlTx get Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
553 bitb #FCTxBrk currently transmitting line Break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
554 bne ReadLoop yes, go skip XON this time...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
555
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
556 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
557 ldb CSReg,x get new Control Status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
558 bitb #CS.TxE Tx data register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
559 beq ReadLoop no, go skip XON this time...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
560 ldb <V.XON
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
561 stb DataReg,x write XON character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
562 ChkHWHS bita #FCRxDTR!FCRxRTS Rx disabled due to DTR or RTS?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
563 beq RxFloClr no, go clear Rx flow control flag(s)...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
564 ldb <Cpy.FR get Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
565 andb #^(F.DTR!F.RTS) clear (enable) DTR and RTS bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
566 stb <Cpy.FR save Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
567 stb CFReg,x set Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
568 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
569
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
570 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
571 ldb StatReg,x get new Status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
572 bitb #Stat.TxE Tx data register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
573 beq ReadLoop no, go skip XON this time...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
574 ldb <V.XON
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
575 stb DataReg,x write XON character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
576 ChkHWHS bita #FCRxDTR!FCRxRTS Rx disabled due to DTR or RTS?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
577 beq RxFloClr no, go clear Rx flow control flag(s)...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
578 ldb CmdReg,x get current Command register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
579 andb #^Cmd.TIRB clear Tx IRQ/RTS/Break control bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
580 orb #TIRB.RTS!Cmd.DTR enable RTS and DTR, disable Tx IRQs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
581 stb CmdReg,x set Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
582 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
583 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
584
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
585 RxFloClr clr <FloCtlRx clear Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
586 ReadChar ldb <V.ERR get accumulated errors, if any
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
587 stb PD.ERR,y set/clear error(s) in path descriptor
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
588 bne ReprtErr error(s), go report it/them...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
589 ldx <RxDatLen get Rx buffer count
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
590 beq ReadSlp none, go sleep while waiting for new Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
591 leax -1,x less character we're about to grab
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
592 stx <RxDatLen save new Rx data count
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
593 ldx <RxBufGet current Rx buffer pickup position
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
594 lda ,x+ get Rx character, set up next pickup position
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
595 cmpx <RxBufEnd end of Rx buffer?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
596 blo SetPckUp no, go keep pickup pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
597 ldx <RxBufPtr get Rx buffer start address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
598 SetPckUp stx <RxBufGet set new Rx data pickup pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
599 puls cc,b,dp,pc recover IRQ/Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
600
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
601
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
602 PrAbtErr ldb #E$PrcAbt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
603 bra ErrExit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
604
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
605 ReprtErr clr <V.ERR clear error status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
606 bitb #DCDLstEr DCD lost error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
607 bne HngUpErr yes, go report it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
608 ldb #E$Read
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
609 ErrExit puls cc restore IRQ enable and Carry status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
610 coma error, set Carry
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
611 puls a,dp,pc restore dummy A (or Tx character), system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
612
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
613 HngUpErr ldb #E$HangUp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
614 lda #PST.DCD DCD lost flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
615 sta PD.PST,y set path status flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
616 bra ErrExit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
617
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
618 NRdyErr ldb #E$NotRdy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
619 bra ErrExit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
620
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
621 UnSvcErr ldb #E$UnkSvc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
622 bra ErrExit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
623
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
624
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
625 WritLoop lda <WritFlag first pass through for this Tx character?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
626 beq WritFast yes, don't sleep yet...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
627 lbsr Sleep1 go sleep for balance of tick...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
628 WritFast inc <WritFlag set "initial write attempt" flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
629 puls cc,a,dp recover IRQ/Carry status, Tx character, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
630
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
631 Writ equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
632 clrb default to no error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
633 pshs cc,a,dp save IRQ/Carry status, Tx character, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
634 lbsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
635 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
636 orcc #IntMasks disable IRQs during error and Tx disable checks
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
637 ldb <V.ERR get accumulated errors, if any
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
638 andb #DCDLstEr DCD lost error? (ignore other errors, if any)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
639 stb PD.ERR,y set/clear error(s) in path descriptor
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
640 bne ReprtErr DCD lost error, go report it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
641
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
642 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
643 ldb <Cpy.CSR get copy of control status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
644 bitb #CS.CTS Tx disabled due to CTS?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
645 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
646 lda <Wrk.Type get software/hardware handshake enables
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
647 bita #DSRFlow DSR/DTR handshake enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
648 beq ChkTxFlo no, go check Tx flow control
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
649 bitb #CS.DSR Tx disabled due to DSR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
650 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
651 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
652
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
653 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
654 lda <Wrk.Type get software/hardware handshake enables
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
655 bita #DSRFlow DSR/DTR handshake enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
656 beq ChkTxFlo no, go check Tx flow control
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
657 ldb <Cpy.Stat get copy of status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
658 bitb <Mask.DSR Tx disabled due to DSR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
659 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
660 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
661 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
662
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
663 ChkTxFlo ldb <FloCtlTx get Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
664 bitb #FCTxBrk currently transmitting line Break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
665 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
666 bita #TxSwFlow Tx software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
667 beq ChkRxFlo no, go check pending Rx flow control
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
668 bitb #FCTxXOff Tx disabled due to received XOFF?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
669 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
670 ChkRxFlo bita #RxSwFlow Rx software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
671 beq ChkTxE no, go check Tx register empty
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
672 ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
673 bitb #FCRxSend XON/XOFF Rx flow control pending?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
674 bne WritLoop yes, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
675 ChkTxE lda 1,s get Tx character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
676
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
677 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
678 ldb CSReg,x get new control status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
679 bitb #CS.TxE Tx register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
680 beq WritLoop no, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
681 sta DataReg,x write Tx character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
682 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
683
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
684 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
685 ldb StatReg,x get new status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
686 bitb #Stat.TxE Tx register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
687 beq WritLoop no, go sleep a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
688 sta DataReg,x write Tx character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
689 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
690 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
691
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
692 clr <WritFlag clear "initial write attempt" flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
693 puls cc,a,dp,pc recover IRQ/Carry status, Tx character, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
694
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
695
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
696 GStt equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
697 clrb default to no error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
698 pshs cc,b,dp save IRQ/Carry status, dummy B, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
699 lbsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
700 ldx PD.RGS,y caller's register stack pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
701 cmpa #SS.EOF
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
702 beq GSExitOK yes, SCF devices never return EOF
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
703 cmpa #SS.Ready
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
704 bne GetScSiz
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
705 ldd <RxDatLen get Rx data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
706 beq NRdyErr none, go report error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
707 tsta more than 255 bytes?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
708 beq SaveLen no, keep Rx data available
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
709 ldb #255 yes, just use 255
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
710 SaveLen stb R$B,x set Rx data available in caller's [B]
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
711 GSExitOK puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
712
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
713 GetScSiz cmpa #SS.ScSiz
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
714 bne GetComSt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
715 ldu PD.DEV,y
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
716 ldu V$DESC,u
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
717 clra
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
718 ldb IT.COL,u
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
719 std R$X,x
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
720 ldb IT.ROW,u
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
721 std R$Y,x
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
722 puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
723
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
724 GetComSt cmpa #SS.ComSt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
725 lbne UnSvcErr no, go report error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
726 ldd <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
727 std R$Y,x
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
728 clra default to DCD and DSR enabled
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
729
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
730 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
731 ldb <Cpy.CSR get current status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
732 bitb #CS.DCD DCD bit set (disabled)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
733 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
734
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
735 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
736 ldb <CpyDCDSR get current DSR+DCD status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
737 bitb <Mask.DCD DCD bit set (disabled)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
738 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
739 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
740
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
741 beq CheckDSR no, go check DSR status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
742 ora #DCDStBit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
743
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
744 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
745 CheckDSR bitb #CS.DSR DSR bit set (disabled)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
746 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
747
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
748 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
749 CheckDSR bitb <Mask.DSR DSR bit set (disabled)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
750 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
751 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
752
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
753 beq SaveCDSt no, go set DCD/DSR status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
754 ora #DSRStBit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
755 SaveCDSt sta R$B,x set 6551 ACIA style DCD/DSR status in caller's [B]
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
756 puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
757
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
758
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
759 BreakSlp ldx #SlpBreak SS.Break duration
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
760 bra TimedSlp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
761 HngUpSlp ldx #SlpHngUp SS.HngUp duration
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
762 bra TimedSlp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
763 Sleep1 ldx #1 give up balance of tick
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
764 TimedSlp pshs cc save IRQ enable status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
765 andcc #Intmasks enable IRQs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
766 os9 F$Sleep
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
767 puls cc,pc restore IRQ enable status, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
768
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
769
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
770 SStt equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
771 clrb default to no error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
772 pshs cc,b,dp save IRQ/Carry status, dummy B, system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
773 lbsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
774 ldx PD.RGS,y
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
775 cmpa #SS.HngUp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
776 bne SetBreak
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
777
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
778 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
779 lda #F.DTR set (disable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
780 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
781 orcc #IntMasks disable IRQs while setting Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
782 ora <Cpy.FR mask in Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
783 sta <Cpy.FR save Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
784 sta CFReg,x set new Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
785 bsr HngUpSlp go sleep for a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
786 lda #^(F.DTR!F.RTS) clear (enable) DTR and RTS bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
787 FRegClr ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
788 anda <Cpy.FR mask in Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
789 ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
790 bitb #FCRxDTR Rx disabled due to DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
791 beq LeaveDTR no, go leave DTR enabled
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
792 ora #F.DTR set (disable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
793 LeaveDTR bitb #FCRxRTS Rx disabled due to RTS?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
794 beq LeaveRTS no, go leave RTS enabled
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
795 ora #F.RTS set (disable) RTS bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
796 LeaveRTS sta <Cpy.FR save Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
797 sta CFReg,x set new Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
798 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
799
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
800 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
801 lda #^Cmd.DTR cleared (disabled) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
802 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
803 orcc #IntMasks disable IRQs while setting Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
804 anda CmdReg,x mask in current Command register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
805 sta CmdReg,x set new Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
806 bsr HngUpSlp go sleep for a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
807 BreakClr lda #^(Cmd.TIRB!Cmd.DTR) clear (disable) DTR and RTS control bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
808 FRegClr ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
809 anda CmdReg,x mask in current Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
810 ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
811 bitb #FCRxDTR Rx disabled due to DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
812 bne LeaveDTR yes, go leave DTR disabled
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
813 ora #Cmd.DTR set (enable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
814 LeaveDTR bitb #FCRxRTS Rx disabled due to RTS?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
815 bne LeaveRTS yes, go leave RTS disabled
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
816 ora #TIRB.RTS enable RTS output
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
817 LeaveRTS ldb <FloCtlTx get Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
818 bitb #FCTxBrk currently transmitting line Break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
819 beq NotTxBrk no, go leave RTS alone...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
820 ora #TIRB.Brk set Tx Break bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
821 NotTxBrk sta CmdReg,x set new Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
822 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
823 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
824
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
825 puls cc,b,dp,pc restore IRQ/Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
826
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
827 SetBreak cmpa #SS.Break Tx line break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
828 bne SetSSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
829
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
830 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
831 ldy <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
832 ldd #FCTxBrk*256+TB.Brk [A]=flow control flag, [B]=Tx break enable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
833 orcc #Intmasks disable IRQs while messing with flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
834 ora <FloCtlTx set Tx break flag bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
835 sta <FloCtlTx save Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
836 stb TBReg,y start Tx line break
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
837 bsr BreakSlp go sleep for a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
838 anda #^FCTxBrk clear Tx break flag bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
839 sta <FloCtlTx save Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
840 clr TBReg,y end Tx line break
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
841 puls cc,b,dp,pc restore IRQ/Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
842 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
843
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
844 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
845 ldy <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
846 ldd #FCTxBrk*256+TIRB.Brk [A]=flow control flag, [B]=Tx break enable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
847 orcc #Intmasks disable IRQs while messing with flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
848 ora <FloCtlTx set Tx break flag bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
849 sta <FloCtlTx save Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
850 orb CmdReg,y set Tx line break bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
851 stb CmdReg,y start Tx line break
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
852 bsr BreakSlp go sleep for a while...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
853 anda #^FCTxBrk clear Tx break flag bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
854 sta <FloCtlTx save Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
855 bra BreakClr go restore RTS output to previous...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
856 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
857 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
858
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
859 SetSSig cmpa #SS.SSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
860 bne SetRelea
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
861 lda PD.CPR,y current process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
862 ldb R$X+1,x LSB of [X] is signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
863 orcc #IntMasks disable IRQs while checking Rx data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
864 ldx <RxDatLen
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
865 bne RSendSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
866 std <SSigPID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
867 puls cc,b,dp,pc restore IRQ/Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
868 RSendSig puls cc restore IRQ/Carry status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
869 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
870 puls a,dp,pc restore dummy A, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
871
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
872 SetRelea cmpa #SS.Relea
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
873 bne SetCDSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
874 leax SSigPID,u point to Rx data signal process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
875 bsr ReleaSig go release signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
876 puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
877
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
878 SetCDSig cmpa #SS.CDSig set DCD signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
879 bne SetCDRel
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
880 lda PD.CPR,y current process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
881 ldb R$X+1,x LSB of [X] is signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
882 std <CDSigPID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
883 puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
884
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
885 SetCDRel cmpa #SS.CDRel release DCD signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
886 bne SetComSt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
887 CDRelSig leax CDSigPID,u point to DCD signal process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
888 bsr ReleaSig go release signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
889 puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
890
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
891 SetComSt cmpa #SS.ComSt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
892 bne SetOpen
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
893 ldd R$Y,x caller's [Y] contains ACIAPAK format type/baud info
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
894 bsr SetPort go save it and set up control/format registers
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
895 ReturnOK puls cc,b,dp,pc restore Carry status, dummy B, system DP, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
896
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
897 SetOpen cmpa #SS.Open
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
898 bne SetClose
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
899 lda R$Y+1,x get LSB of caller's [Y]
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
900 deca real SS.Open from SCF? (SCF sets LSB of [Y] = 1)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
901 bne ReturnOK no, go do nothing but return OK...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
902
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
903 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
904 lda #^(F.DTR!F.RTS) clear (enable) DTR and RTS bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
905 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
906
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
907 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
908 lda #TIRB.RTS enabled DTR and RTS outputs
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
909 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
910 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
911
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
912 orcc #IntMasks disable IRQs while setting Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
913 lbra FRegClr go enable DTR and RTS (if not disabled due to Rx flow control)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
914
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
915 SetClose cmpa #SS.Close
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
916 lbne UnSvcErr no, go report error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
917 lda R$Y+1,x real SS.Close from SCF? (SCF sets LSB of [Y] = 0)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
918 bne ReturnOK no, go do nothing but return OK...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
919 leax SSigPID,u point to Rx data signal process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
920 bsr ReleaSig go release signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
921 bra CDRelSig go release DCD signal, return from there...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
922
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
923 ReleaSig pshs cc save IRQ enable status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
924 orcc #IntMasks disable IRQs while releasing signal
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
925 lda PD.CPR,y get current process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
926 suba ,x same as signal process ID?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
927 bne NoReleas no, go return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
928 sta ,x clear this signal's process ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
929 NoReleas puls cc,pc restore IRQ enable status, return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
930
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
931 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
932 SetPort pshs cc save IRQ enable and Carry status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
933 orcc #IntMasks disable IRQs while setting up DACIA registers
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
934 std <Wrk.Type save type/baud in data area
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
935 lsra *shift parity bits into
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
936 lsra *position for 65C52's
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
937 lsra *format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
938 anda #F.Par clear all except parity bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
939 pshs a save parity temporarily
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
940 comb translate word length bits to 65C52's word length code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
941 andb #F.DatBit clear all except word length bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
942 orb ,s+ mask in parity and clean up stack
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
943 lda <Wrk.Baud get baud information
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
944 anda #BaudRate clear all but baud rate bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
945 leax BaudTabl,pcr
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
946 lda a,x get baud rate setting
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
947 pshs a save it temporarily
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
948 lda <Wrk.Baud get stop bit(s) information
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
949 lsra *shift stop bit into position
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
950 lsra *for 65C52's control register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
951 anda #C.StpBit clear all except stop bit code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
952 ora ,s+ mask in baud rate and clean up stack
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
953 pshs d save stopbits/baudrate and wordlength/parity temporarily
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
954 ldd <Cpy.CR get old control/format register copies
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
955 anda #^(C.StpBit!C.Baud) clear stop bit and baud rate code bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
956 ora ,s+ mask in stop bit(s) and baud rate
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
957 andb #^(F.DatBit!F.Par) clear word length and parity code bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
958 orb ,s+ mask in word length and parity
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
959 ldx <V.PORT get port address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
960 std <Cpy.CR save control/format register copies
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
961 sta CFReg,x set control register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
962 stb CFReg,x set format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
963 puls cc,pc recover IRQ enable and Carry status, return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
964 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
965
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
966 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
967 SetPort pshs cc save IRQ enable and Carry status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
968 orcc #IntMasks disable IRQs while setting up ACIA registers
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
969 std <Wrk.Type save type/baud in data area
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
970 leax BaudTabl,pcr
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
971 andb #BaudRate clear all but baud rate bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
972 ldb b,x get baud rate setting
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
973 pshs b save it temporarily
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
974 ldb <Wrk.Baud get baud info again
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
975 andb #^(Ctl.RxCS!Ctl.Baud) clear clock source + baud rate code bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
976 orb ,s+ mask in clock source + baud rate and clean up stack
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
977 ldx <V.PORT get port address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
978 anda #Cmd.Par clear all except parity bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
979 pshs a save new command register contents temporarily
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
980 lda CmdReg,x get current command register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
981 anda #^Cmd.Par clear parity control bits
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
982 ora ,s+ mask in new parity
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
983 std CmdReg,x set command+control registers
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
984 puls cc,pc recover IRQ enable and Carry status, return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
985 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
986 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
987
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
988 SetDP pshs u save our data pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
989 puls dp set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
990 leas 1,s clean up stack
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
991 rts
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
992
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
993 AccumErr ora <V.ERR
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
994 sta <V.ERR
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
995 rts
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
996
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
997
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
998 ifeq A6552-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
999 IRQSvc equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1000 pshs dp save system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1001 bsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1002 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1003 ldb CSReg,x get current Control/Status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1004 std <Cpy.ISR save ISR (from D.Poll check) and CSR copies
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1005 bita #ISE.FOB!ISE.Par FRM/OVR/BRK or Parity error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1006 beq ChkRDRF no, go check Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1007 tst DataReg,x read Rx data register to clear DACIA error flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1008 bitb #CS.Break Rx line break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1009 beq ChkParty no, go check if parity error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1010 lda <V.QUIT default to keyboard quit ("Break") code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1011 bra RxBreak go pretend we've received V.QUIT character...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1012
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1013 ChkParty anda #ISE.Par parity error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1014 beq ChkFrame no, go check framing error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1015 lda #ParityEr mark parity error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1016 ChkFrame bitb #CS.Frame framing error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1017 beq ChkOvRun no, go check overrun error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1018 ora #FrmingEr mark Framing error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1019 ChkOvRun tsta any other error flag(s) set?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1020 bne SaveErrs yes, go save them...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1021 ora #OvrFloEr must be overrun error, mark it
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1022 SaveErrs bsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1023 lbra ChkTrDCD go check if DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1024
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1025 ChkRDRF bita #ISE.RxF Rx data?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1026 lbeq ChkTrDCD no, go check DCD transition
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1027 lda DataReg,x get Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1028 RxBreak beq SavRxDat its a null, go save it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1029 clr <SigSent clear signal sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1030 cmpa <V.INTR interrupt?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1031 bne Chk.Quit no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1032 ldb #S$Intrpt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1033 bra SendSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1034 Chk.Quit cmpa <V.QUIT abort?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1035 bne Chk.PChr no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1036 ldb #S$Abort
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1037 SendSig pshs a save Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1038 lda <V.LPRC get last process' ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1039 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1040 puls a recover Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1041 stb <SigSent set signal sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1042 bra SavRxDat go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1043 Chk.PChr cmpa <V.PCHR pause?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1044 bne Chk.Flow no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1045 ldx <V.DEV2 attached device defined?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1046 beq SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1047 sta V.PAUS,x yes, pause attached device
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1048 bra SavRxDat go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1049 Chk.Flow ldb <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1050 bitb #TxSwFlow Tx data software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1051 beq SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1052 cmpa <V.XON XON?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1053 bne Chk.XOff no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1054 ldb #^FCTxXOff clear XOFF received bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1055 andb <FloCtlTx clear software Tx flow control flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1056 bra SetTxFlo go save new Tx flow control flags...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1057 Chk.XOff cmpa <V.XOFF XOFF?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1058 bne SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1059 ldb #FCTxXOff set XOFF received bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1060 orb <FloCtlTx set software Tx flow control flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1061 SetTxFlo stb <FloCtlTx save new Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1062 lbra ChkTrDCD go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1063 SavRxDat ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1064 andb #^FCRxSend clear possible pending XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1065 stb <FloCtlRx save Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1066 ldy <RxBufPut get Rx buffer input pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1067 ldx <RxDatLen Rx get Rx buffer data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1068 cmpx <RxBufSiz Rx buffer already full?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1069 blo NotOvFlo no, go skip overflow error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1070 lda #OvrFloEr mark Rx buffer overflow
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1071 lbsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1072 bra DisRxFlo go ensure Rx is disabled (if possible)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1073 NotOvFlo sta ,y+ save Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1074 cmpy <RxBufEnd end of Rx buffer?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1075 blo SetLayDn no, go keep laydown pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1076 ldy <RxBufPtr get Rx buffer start address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1077 SetLayDn sty <RxBufPut set new Rx data laydown pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1078 leax 1,x one more byte in Rx buffer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1079 stx <RxDatLen save new Rx data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1080 cmpx <RxBufMax at or past maximum (XOFF) fill point?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1081 blo SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1082 DisRxFlo lda <Wrk.XTyp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1083 ldb <Cpy.FR get Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1084 bita #ForceDTR forced DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1085 bne DisRxRTS yes, go check RTS disable...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1086 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1087 bita #DSRFlow DSR/DTR flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1088 beq DisRxRTS no, go check RTS disable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1089 lda <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1090 ora #FCRxDTR mark Rx disabled by DTR
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1091 sta <FloCtlRx save new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1092 orb #F.DTR set (disable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1093 DisRxRTS lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1094 bita #RTSFlow CTS/RTS flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1095 beq NewRxFlo no, go set new Rx flow control...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1096 lda <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1097 ora #FCRxRTS mark Rx disabled by RTS
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1098 sta <FloCtlRx save new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1099 orb #F.RTS set (disable) RTS bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1100 NewRxFlo ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1101 stb <Cpy.FR save Format register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1102 stb CFReg,x set/clear DTR and RTS in Format register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1103 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1104 bita #RxSwFlow Rx data software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1105 beq SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1106 lda <V.XOFF XOFF character defined?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1107 beq SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1108 ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1109 bitb #FCRxSent XOFF already sent?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1110 bne SgnlRxD yes, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1111 orb #FCRxSend set send XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1112 stb <FloCtlRx set new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1113 ldb <Cpy.CSR get Control status register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1114 bitb #CS.TxE Tx data register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1115 beq SgnlRxD no, go skip XOFF this time...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1116 sta DataReg,x write XOFF character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1117 ldb #FCRxSent set XOFF sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1118 orb <FloCtlRx mask in current Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1119 andb #^FCRxSend clear send XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1120 stb <FloCtlRx save new flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1121 SgnlRxD ldb <SigSent already sent abort/interrupt signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1122 bne ChkTrDCD yes, go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1123 lda <SSigPID Rx data signal process ID?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1124 beq ChkTrDCD none, go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1125 ldb <SSigSig Rx data signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1126 clr <SSigPID clear Rx data signal
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1127 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1128
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1129 ChkTrDCD ldd <Cpy.ISR get IRQ and Control Status copies
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1130 bita #ISE.DCD DCD transition?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1131 beq CkSuspnd no, go check for suspended process...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1132 bitb #CS.DCD DCD disabled now?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1133 beq SgnlDCD no, go check DCD signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1134 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1135 bita #MdmKill modem kill enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1136 beq SgnlDCD no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1137 ldx <V.PDLHd path descriptor list header
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1138 beq StCDLost no list, go set DCD lost error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1139 lda #PST.DCD DCD lost flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1140 PDListLp sta PD.PST,x set path status flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1141 ldx PD.PLP,x get next path descriptor in list
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1142 bne PDListLp not end of list, go do another...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1143 StCDLost lda #DCDLstEr DCD lost error flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1144 lbsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1145 SgnlDCD lda <CDSigPID get process ID, send a DCD signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1146 beq CkSuspnd no, go check for suspended process...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1147 ldb <CDSigSig get DCD signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1148 clr <CDSigPID clear DCD signal
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1149 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1150
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1151 CkSuspnd clrb clear Carry (for exit) and LSB of process descriptor address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1152 lda <V.WAKE anybody waiting? ([D]=process descriptor address)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1153 beq IRQExit no, go return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1154 stb <V.WAKE mark I/O done
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1155 tfr d,x copy process descriptor pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1156 lda P$State,x get state flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1157 anda #^Suspend clear suspend state
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1158 sta P$State,x save state flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1159 IRQExit puls dp,pc recover system DP, return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1160 else
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1161
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1162 ifeq A6551-true
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1163 IRQSvc equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1164 pshs dp save system DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1165 bsr SetDP go set our DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1166 ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1167 ldb StatReg,x get current Status register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1168 stb <Cpy.Stat save Status register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1169 bitb #Stat.Err error(s)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1170 beq ChkRDRF no, go check Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1171 tst DataReg,x read Rx data register to clear ACIA error flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1172 bitb #Stat.Frm framing error (assume Rx line Break)?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1173 beq ChkParty no, go check if parity error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1174 lda <V.QUIT default to keyboard quit ("Break") code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1175 bra RxBreak go pretend we've received V.QUIT character...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1176
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1177 ChkParty clra clear old IRQ status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1178 bitb #Stat.Par parity error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1179 beq ChkOvRun no, go check overrun error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1180 ora #ParityEr mark parity error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1181 ChkOvRun bita #Stat.Ovr overrun error?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1182 beq SaveErrs no, go save errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1183 ora #OvrFloEr mark overrun error
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1184 SaveErrs bsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1185 lbra ChkTrDCD go check if DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1186
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1187 ChkRDRF bitb #Stat.RxF Rx data?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1188 lbeq ChkTrDCD no, go check DCD transition
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1189 lda DataReg,x get Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1190 RxBreak beq SavRxDat its a null, go save it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1191 clr <SigSent clear signal sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1192 cmpa <V.INTR interrupt?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1193 bne Chk.Quit no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1194 ldb #S$Intrpt
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1195 bra SendSig
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1196 Chk.Quit cmpa <V.QUIT abort?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1197 bne Chk.PChr no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1198 ldb #S$Abort
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1199 SendSig pshs a save Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1200 lda <V.LPRC get last process' ID
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1201 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1202 puls a recover Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1203 stb <SigSent set signal sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1204 bra SavRxDat go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1205 Chk.PChr cmpa <V.PCHR pause?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1206 bne Chk.Flow no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1207 ldx <V.DEV2 attached device defined?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1208 beq SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1209 sta V.PAUS,x yes, pause attached device
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1210 bra SavRxDat go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1211 Chk.Flow ldb <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1212 bitb #TxSwFlow Tx data software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1213 beq SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1214 cmpa <V.XON XON?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1215 bne Chk.XOff no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1216 ldb #^FCTxXOff clear XOFF received bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1217 andb <FloCtlTx clear software Tx flow control flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1218 bra SetTxFlo go save new Tx flow control flags...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1219 Chk.XOff cmpa <V.XOFF XOFF?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1220 bne SavRxDat no, go save Rx data...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1221 ldb #FCTxXOff set XOFF received bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1222 orb <FloCtlTx set software Tx flow control flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1223 SetTxFlo stb <FloCtlTx save new Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1224 lbra ChkTrDCD go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1225 SavRxDat ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1226 andb #^FCRxSend clear possible pending XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1227 stb <FloCtlRx save Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1228 ldy <RxBufPut get Rx buffer input pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1229 ldx <RxDatLen Rx get Rx buffer data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1230 cmpx <RxBufSiz Rx buffer already full?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1231 blo NotOvFlo no, go skip overflow error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1232 lda #OvrFloEr mark Rx buffer overflow
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1233 lbsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1234 bra DisRxFlo go ensure Rx is disabled (if possible)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1235 NotOvFlo sta ,y+ save Rx data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1236 cmpy <RxBufEnd end of Rx buffer?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1237 blo SetLayDn no, go keep laydown pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1238 ldy <RxBufPtr get Rx buffer start address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1239 SetLayDn sty <RxBufPut set new Rx data laydown pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1240 leax 1,x one more byte in Rx buffer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1241 stx <RxDatLen save new Rx data length
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1242 cmpx <RxBufMax at or past maximum fill point?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1243 blo SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1244 DisRxFlo ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1245 lda <Wrk.XTyp
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1246 ldb CmdReg,x get current Command register contents
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1247 bita #ForceDTR forced DTR?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1248 bne DisRxRTS yes, go check RTS disable...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1249 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1250 bita #DSRFlow DSR/DTR flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1251 beq DisRxRTS no, go check RTS disable
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1252 lda <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1253 ora #FCRxDTR mark Rx disabled by DTR
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1254 sta <FloCtlRx save new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1255 andb #^Cmd.DTR clear (disable) DTR bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1256 DisRxRTS lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1257 bita #RTSFlow CTS/RTS flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1258 beq NewRxFlo no, go set new Rx flow control...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1259 lda <FloCtlTx get Tx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1260 bita #FCTxBrk currently transmitting line Break?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1261 bne NewRxFlo yes, go set new Rx flow control...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1262 lda <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1263 ora #FCRxRTS mark Rx disabled by RTS
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1264 sta <FloCtlRx save new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1265 andb #^Cmd.TIRB clear Tx IRQ/RTS/Break control bits (disable RTS)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1266 NewRxFlo stb CmdReg,x set/clear DTR and RTS in Command register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1267 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1268 bita #RxSwFlow Rx software flow control enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1269 beq SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1270 lda <V.XOFF XOFF character defined?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1271 beq SgnlRxD no, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1272 ldb <FloCtlRx get Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1273 bitb #FCRxSent XOFF already sent?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1274 bne SgnlRxD yes, go check Rx data signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1275 orb #FCRxSend set send XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1276 stb <FloCtlRx set new Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1277 ldb StatReg,x get new Status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1278 bitb #Stat.TxE Tx data register empty?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1279 beq SgnlRxD no, go skip XOFF this time...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1280 sta DataReg,x write XOFF character
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1281 ldb #FCRxSent set XOFF sent flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1282 orb <FloCtlRx mask in current Rx flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1283 andb #^FCRxSend clear send XOFF flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1284 stb <FloCtlRx save new flow control flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1285 SgnlRxD ldb <SigSent already sent abort/interrupt signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1286 bne ChkTrDCD yes, go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1287 lda <SSigPID Rx data signal process ID?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1288 beq ChkTrDCD none, go check DCD transition...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1289 ldb <SSigSig Rx data signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1290 clr <SSigPID clear Rx data signal
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1291 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1292
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1293 ChkTrDCD ldx <V.PORT
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1294 lda <Cpy.Stat get Status register copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1295 tfr a,b copy it...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1296 eora <CpyDCDSR mark changes from old DSR+DCD status copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1297 andb #Stat.DSR!Stat.DCD clear all but DSR+DCD status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1298 stb <CpyDCDSR save new DSR+DCD status copy
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1299 bita <Mask.DCD DCD transition?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1300 beq CkSuspnd no, go check for suspended process...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1301 bitb <Mask.DCD DCD disabled now?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1302 beq SgnlDCD no, go check DCD signal...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1303 lda <Wrk.Type
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1304 bita #MdmKill modem kill enabled?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1305 beq SgnlDCD no, go on...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1306 ldx <V.PDLHd path descriptor list header
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1307 beq StCDLost no list, go set DCD lost error...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1308 lda #PST.DCD DCD lost flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1309 PDListLp sta PD.PST,x set path status flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1310 ldx PD.PLP,x get next path descriptor in list
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1311 bne PDListLp not end of list, go do another...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1312 StCDLost lda #DCDLstEr DCD lost error flag
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1313 lbsr AccumErr go save accumulated errors...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1314 SgnlDCD lda <CDSigPID get process ID, send a DCD signal?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1315 beq CkSuspnd no, go check for suspended process...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1316 ldb <CDSigSig get DCD signal code
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1317 clr <CDSigPID clear DCD signal
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1318 os9 F$Send
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1319
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1320 CkSuspnd clrb clear Carry (for exit) and LSB of process descriptor address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1321 lda <V.WAKE anybody waiting? ([D]=process descriptor address)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1322 beq IRQExit no, go return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1323 stb <V.WAKE mark I/O done
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1324 tfr d,x copy process descriptor pointer
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1325 lda P$State,x get state flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1326 anda #^Suspend clear suspend state
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1327 sta P$State,x save state flags
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1328 IRQExit puls dp,pc recover system DP, return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1329 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1330 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1331
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1332
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1333 emod
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1334 ModSize equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1335 end
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1336