annotate level1/modules/clock.asm @ 1071:853a796a1bcd

Removed logbook
author boisy
date Mon, 31 Mar 2003 14:10:56 +0000
parents da4002e207e3
children 4e235f213651
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1 ********************************************************************
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2 * Clock - OS-9 Level One V2 Clock module
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3 *
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4 * $Id$
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5 *
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6 * NOTE: This clock is TOTALLY VALID for ALL DATES between 1900-2155
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7 *
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8 * Ed. Comments Who YY/MM/DD
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9 * ------------------------------------------------------------------
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10 * 5 Tandy/Microware original version
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11 * 6 Modified to handle leap years properly for BGP 99/05/03
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12 * 1900 and 2100 A.D.
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13 * Added TC^3 SCSI/B&B RTC Clock Support BGP 02/05/14
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15 nam Clock
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16 ttl OS-9 Level One V2 Clock module
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17
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18 IFP1
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19 use defsfile
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20 ENDC
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21
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22 tylg set Systm+Objct
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23 atrv set ReEnt+rev
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24 rev set $1
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668388823050 Fixed headers to be consistent
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25 edition set 6
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26
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27 mod eom,name,tylg,atrv,ClkEnt,RTC.Base
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28
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29 size equ .
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30
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31 name fcs /Clock/
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32 fcb edition
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33
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34 * If no RTC defines are set, then this is a software clock
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35 IFEQ RTCBB+RTCTC3
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36 SOFT set 1
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37 ENDC
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38
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39 IFNE RTCBB
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40 MPIFlag set 1
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41 SlotSlct set $22
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42 RTC.Base equ $FF5C
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43 ENDC
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44 IFNE RTCTC3
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45 RTC.Base equ $FF7C
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46 ENDC
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47 IFNE SOFT
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48 RTC.Base equ size
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49 ENDC
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50
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51 IFNE RTCBB+RTCTC3
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52 RTC.Zero equ -4 Send zero bit by writing this offset
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53 RTC.One equ -3 Send one bit by writing this offset
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54 RTC.Read equ 0 Read data from this offset
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55 ENDC
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56
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57 SysTbl fcb F$Time
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58 fdb FTime-*-2
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59 fcb F$VIRQ
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60 fdb FVIRQ-*-2
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61
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62 IFEQ SOFT
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63
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64 fcb F$STime
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65 fdb FSTime-*-2
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66
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67 ENDC
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68
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69 fcb $80
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70
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71 IFNE SOFT
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72 * table of days of the month
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73 MonthChk fcb 00
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74 fcb 31 January
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75 fcb 28 February
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76 fcb 31 March
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77 fcb 30 April
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78 fcb 31 May
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79 fcb 30 June
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80 fcb 31 July
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81 fcb 31 August
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82 fcb 30 September
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83 fcb 31 October
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84 fcb 30 November
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85 fcb 31 December
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86
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87 ELSE
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89 FSTime ldx R$X,u
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90 ldd ,x
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91 std <D.Year
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92 ldd 2,x
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93 std <D.Day
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94 ldd 4,x
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95 std <D.Min
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96 andcc #^Carry
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97
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98 ENDC
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99
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100 IFNE RTCBB+RTCTC3
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101
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102 pshs u,y,cc
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103 leay SendBCD,pcr Send bytes of clock
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104 lbra TfrTime
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105 *
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106 * Update time from B&B/TC3 RTC
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107 *
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108 UpdTime pshs u,y,cc
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109 leay ReadBCD,pcr Read bytes of clock
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110
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111 TfrTime orcc #IntMasks turn off interrupts
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112 ldu M$Mem,pcr Get base address
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113
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114 IFNE MPIFlag
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115 ldb >MPI.Slct Select slot
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116 pshs b
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117 andb #$F0
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118 orb SlotSlct,pcr
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119 stb >MPI.Slct
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120 ENDC
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121
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122 lbsr SendMsg Initialize clock
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123 ldx #D.Sec
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124 ldb #8 Tfr 8 bytes
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125
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126 tfrloop jsr ,y Tfr 1 byte
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127 bitb #$03
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128 beq skipstuf Skip over day-of-week, etc.
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129 leax -1,x
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130 skipstuf decb
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131 bne tfrloop
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132
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133 IFNE MPIFlag
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134 puls b
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135 stb >MPI.Slct restore MPAK slot
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136 ENDC
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137
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138 puls u,y,cc,pc
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139
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140 ClkMsg fcb $C5,$3A,$A3,$5C,$C5,$3A,$A3,$5C
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141 * Enable clock with message $C53AA35CC53AA35C
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142 SendMsg lda RTC.Read,u Send Initialization message to clock
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143 leax <ClkMsg,pcr
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144 ldb #8
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145 msgloop lda ,x+
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146 bsr SendByte
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147 decb
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148 bne msgloop
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149 rts
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150
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151 SendBCD pshs b Send byte to clock, first converting to BCD
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152 bitb #$03
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153 bne BCDskip Send zero for day-of-week, etc.
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154 lda #0
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155 bra SndBCDGo
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156 BCDskip lda ,x
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157 SndBCDGo tfr a,b
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158 bra binenter
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159 binloop adda #6
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160 binenter subb #10
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161 bhs binloop
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162 puls b
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163 SendByte coma Send one byte to clock
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164 rora
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165 bcc sendone
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166 sendzero tst RTC.Zero,u
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167 lsra
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168 bcc sendone
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169 bne sendzero
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170 rts
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171 sendone tst RTC.One,u
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172 lsra
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173 bcc sendone
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174 bne sendzero
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175 rts
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176
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177 ReadBCD pshs b
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178 ldb #$80 High bit will rotate out after we read 8 bits
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179 readbit lda RTC.Read,u Read a bit
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180 lsra
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181 rorb Shift it into B
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182 bcc readbit Stop when marker bit appears
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183 tfr b,a
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184 bra BCDEnter Convert BCD number to Binary
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185 BCDLoop subb #6 by subtracting 6 for each $10
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186 BCDEnter suba #$10
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187 bhs BCDLoop
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188 stb ,x
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189 puls b,pc
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190 ENDC
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191
1000
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192 IFNE RTCDriveWire
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193 rts
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194
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195 use bbwrite.asm
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196
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197 UpdTime pshs y,x,cc
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198 lda #'# Time packet
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199 orcc #IntMasks Disable interrupts
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200 lbsr SerWrite
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201 bsr SerRead Read year byte
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202 bcs UpdLeave
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203 sta <D.Year
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204 bsr SerRead Read month byte
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205 bcs UpdLeave
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206 sta <D.Month
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207 bsr SerRead Read day byte
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208 bcs UpdLeave
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209 sta <D.Day
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210 bsr SerRead Read hour byte
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211 bcs UpdLeave
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212 sta <D.Hour
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213 bsr SerRead Read minute byte
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214 bcs UpdLeave
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215 sta <D.Min
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216 bsr SerRead Read second byte
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217 bcs UpdLeave
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218 sta <D.Sec
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219 bsr SerRead Read day of week (0-6) byte
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220 UpdLeave puls cc,x,y,pc
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221
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222 use bbread.asm
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223
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224 ENDC
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225
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226
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227 *
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228 * Clock IRQ Entry Point
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229 *
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230 ClockIRQ clra
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231 tfr a,dp set direct page to zero
506
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232 lda PIA.U4+3 get hw byte
0
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233 bmi L0032 branch if sync flag on
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234 jmp [>D.SvcIRQ]
506
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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235 L0032 lda PIA.U4+2 clear interrupt?
0
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236 dec <D.Tick decrement tick counter
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237 bne L007F go around if not zero
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238 ldd <D.Min get minutes/seconds
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239 * Seconds increment
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240 incb increment seconds
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241 cmpb #60 full minute?
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242 bcs L0079 nope...
506
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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243
1000
da4002e207e3 Added DriveWire support to clock module
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244 IFNE RTCBB+RTCTC3+RTCDriveWire
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245 *
da4002e207e3 Added DriveWire support to clock module
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246 * Hardware clock code
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247 *
506
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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248
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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249 lbsr UpdTime
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250 bra L007B
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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251
1000
da4002e207e3 Added DriveWire support to clock module
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252 ELSE
da4002e207e3 Added DriveWire support to clock module
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253 *
da4002e207e3 Added DriveWire support to clock module
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254 * Software clock code
da4002e207e3 Added DriveWire support to clock module
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255 *
0
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256 * Minutes increment
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257 inca else increment minute
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258 cmpa #60 full hour?
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259 bcs L0078 nope...
506
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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260 ldd <D.Day else increment day
0
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261 * Hour increment
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262 incb increment hour
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263 cmpb #24 past 23rd hour?
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264 bcs L0075 branch if not
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265 * Day increment
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266 inca else increment day
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267 leax >MonthChk,pcr
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268 ldb <D.Month
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269 * cmpb #3 is this February?
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270 * bne L005F
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271 * ldb <D.Year check year
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272 * beq L005F if century, it's a leap year
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273 * andb #$03 leap year? (divisible by 4)
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274 * beq L0060 nope
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275 *L005F inca
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276 *L0060 ldb <D.Month get month
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277 cmpa b,x compare days to max days
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278 bls L0074 branch if ok
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279 cmpb #2 is this February?
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280 bne L006X if not, go on to year/month
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281 * Leap year cases checked here
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282 ldb <D.Year else check for leap year cases
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283 beq L006X branch if year 1900
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284 cmpb #200 is it 1900+200 (2100)?
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285 beq L006X if so, branch
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286 andb #$03 see if 2^4 bit set (leap year)
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287 cmpd #$1D00 29th on leap year?
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diff changeset
288 beq L0074 it's a leap year...
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289 L006X ldd <D.Year else get year and month
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290 * Month increment
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291 incb increment month
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292 cmpb #13 past December?
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293 bcs L0070 branch if not
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294 * Year increment
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295 inca else in year
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296 ldb #1 and start month in January
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297 L0070 std <D.Year update year/month
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298 lda #1 new month, first day
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299 L0074 clrb hour 0
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300 L0075 std <D.Day update day/hour
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301 clra 0 minutes
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302 L0078 clrb 0 seconds
506
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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diff changeset
303
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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parents: 201
diff changeset
304 ENDC
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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parents: 201
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305
0
6641a883d6b0 Initial revision
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306 L0079 std <D.Min update min/sec
506
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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parents: 201
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307 L007B lda <D.TSec
0
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308 sta <D.Tick
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309 L007F clra
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310 pshs a
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311 ldy <D.CLTB
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312 bra L009E
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313 L0087 ldd ,x
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314 subd #$0001
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315 bne L009C
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316 lda #$01
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317 sta ,s
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318 lda $04,x
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319 beq L00B8
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320 L0096 ora #$01
6641a883d6b0 Initial revision
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321 sta $04,x
6641a883d6b0 Initial revision
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322 ldd $02,x
6641a883d6b0 Initial revision
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323 L009C std ,x
6641a883d6b0 Initial revision
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324 L009E ldx ,y++
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325 bne L0087
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326 lda ,s+
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327 beq L00B4
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328 ldx <D.Proc
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329 beq L00AE
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330 tst P$State,x
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331 bpl L00BC branch if sysstate not set
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332 L00AE jsr [>D.Poll]
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333 bcc L00AE
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334 L00B4 jmp [>D.AltIRQ]
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335 L00B8 bsr L00DD
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336 bra L0096
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337 L00BC leay >L00C4,pcr
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338 jmp [>D.URtoSs]
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339 L00C4 jsr [>D.Poll]
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340 bcc L00C4
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341 ldx <D.Proc
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342 ldb P$State,x
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343 andb #^SysState turn off sysstate bit
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344 stb P$State,x
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345 ldd <P$SWI2,x
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346 std <D.SWI2
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347 ldd <D.UsrIRQ
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348 std <D.SvcIRQ
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349 bra L00B4
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350 L00DD pshs y,x
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351 L00DF ldx ,y++
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352 stx -$04,y
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353 bne L00DF
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354 puls y,x
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355 leay -2,y
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356 rts
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357
87
39ea0a63ce31 F$VIRQ in place of Unknown label
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parents: 62
diff changeset
358 FVIRQ pshs cc
0
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359 orcc #FIRQMask+IRQMask
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360 ldy <D.CLTB
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361 ldx <D.Init
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362 ldb PollCnt,x
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363 ldx R$X,u
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364 beq L0118
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365 tst ,y
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366 beq L010C
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367 subb #$02
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368 lslb
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369 leay b,y
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370 tst ,y
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371 bne L0128
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372 L0106 tst ,--y
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373 beq L0106
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374 leay $02,y
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375 L010C ldx R$Y,u
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376 stx ,y
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377 ldy R$D,u
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378 sty ,x
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379 bra L0124
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380 L0118 leax R$Y,u
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381 L011A tst ,y
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382 beq L0124
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383 cmpx ,y++
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384 bne L011A
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385 bsr L00DD
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386 L0124 puls cc
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387 clrb
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388 rts
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389 L0128 puls cc
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parents:
diff changeset
390 comb
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parents:
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391 ldb #E$Poll
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parents:
diff changeset
392 rts
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parents:
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393
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394 ClkEnt equ *
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395 pshs dp,cc
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396 clra
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397 tfr a,dp
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parents:
diff changeset
398
62
0817702b8a2e clock.asm now references TPS, defsfile references systype
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parents: 0
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399 lda #TPS
0
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parents:
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400
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401 sta <D.TSec
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402 sta <D.Tick
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parents:
diff changeset
403
62
0817702b8a2e clock.asm now references TPS, defsfile references systype
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parents: 0
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404 lda #TPS/10
0
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parents:
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405
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parents:
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406 sta <D.TSlice
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parents:
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407 sta <D.Slice
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parents:
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408 orcc #FIRQMask+IRQMask mask ints
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409 leax >ClockIRQ,pcr
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410 stx <D.IRQ
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411 * install system calls
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parents:
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412 leay >SysTbl,pcr
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parents:
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413 os9 F$SSvc
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414 ldx #PIA.U4
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415 clra
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416 sta 1,x change PIA.U4 side A to DDR
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417 sta ,x clear PIA.U4 side A
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418 sta 3,x change PIA.U4 side B to DDR
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419 coma complement A side A
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420 sta 2,x write all 1's to PIA.U4 side B
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421 lda #$34
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422 sta 1,x PIA.U4 side A to I/O reg
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423 lda #$3F
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424 sta 3,x PIA.U4 side B to I/O reg
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425 lda 2,x
506
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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426
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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427 IFEQ SOFT
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428
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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429 lbsr UpdTime Update time from RTC if one
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430
4f81e616d397 clock.asm now has B&B and TC^3 clock code
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431 ENDC
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432
0
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433 puls pc,dp,cc
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434
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435 * F$Time system call code
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436 FTime ldx R$X,u
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437 ldd <D.Year
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438 std ,x
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439 ldd <D.Day
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440 std 2,x
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441 ldd <D.Min
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442 std 4,x
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443 clrb
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444 rts
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445
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446 emod
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447 eom equ *
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448 end