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2602
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1 IFEQ H6309-1
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2576
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2
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3 *******************************************************
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4 *
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5 * DWRead - 6309 native Turbo Edition 115k / 230k
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6 * Receive a response from the DriveWire server.
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7 * Times out if no data received within 1.3 (0.66) seconds.
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8 *
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9 * THIS VERSION REQUIRES ONE OR MORE SYNC BYTES
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10 * WHERE THE THE FINAL SYNC BYTE IS $C0 AND ANY
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11 * PRECEDING SYNC BYTES ARE $FF.
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12 *
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13 * THE DATA BYTES MUST BE TRANSMITTED IN REVERSE
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14 * BIT ORDER (MOST-SIGNIFICANT FIRST).
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15 *
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16 * Serial data format: 8-N-2 (TWO STOP BITS MANDATORY)
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17 *
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18 * Entry:
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19 * X = storage address for incoming data
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20 * Y = number of bytes requested
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21 *
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22 * Exit:
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23 * CC = Z set on success, cleared on timeout
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24 * Y = checksum
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25 * U is preserved
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26 * All others clobbered
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27 *
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28 BBIN equ $FF22 ; bit banger input port
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29
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30 DWRead clra ; ACCA = 0, clear Carry
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31 pshs u,dp,a,cc ; save registers (A allocates space for status)
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32 orcc #$50 ; mask interrupts
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33 deca ; select hardware page..
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34 tfr a,dp ; ..as the direct page
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35 ldu #BBIN ; point U at input port
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36 tfr y,w ; W = request count
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37 leay ,x ; Y = storage ptr
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38 ldx #0 ; initialize timeout counter
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39 stx <$FF92 ; disable GIME interrupts
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40 ldd <$FF92 ; clear spurious interrupts
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41
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42 * Turn off PIA interrupt sources except for the CD input pin.
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43 lda <$FF01 ; save PIA 0 controls on the stack
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44 ldb <$FF03
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45 pshs d
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46 andd #$FCFC ; clear IRQ enables
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47 sta <$FF01 ; set new control state for PIA 0
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48 stb <$FF03
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49 lda <$FF00 ; ensure that IRQ outputs are cleared
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50 ldb <$FF02
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51 lda <$FF21 ; save PIA 1 controls on the stack
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52 ldb <$FF23
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53 pshs d
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54 andd #$FCFC ; clear FIRQ enables
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55 inca ; set CD FIRQ enable
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56 sta <$FF21 ; set new control state for PIA 1
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57 stb <$FF23
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58
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59 * Wait for Sync Byte(s) or Timeout
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60 sync1 ldd #$0102 ; ACCA = serial in mask, ACCB = shift counter
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61 sync2 bita ,u ; sample input
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62 beq sync3 ; branch if low
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63 leax -1,x ; decrement timeout counter
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64 bne sync1 ; loop if timeout has not expired
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65 bra rxDone ; exit due to timeout
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66 sync3 lsrb ; have there been 2 consecutive low samples?
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67 bcc sync2 ; keep waiting if no
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68 ldx #0 ; initialize checksum
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69 sync4 bita ,u ; sample input
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70 bne rxByte ; branch if input has returned hi
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71 rorb ; bump secondary timeout counter
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72 bcc sync4 ; branch if not timeout
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73 bra rxDone ; exit due to timeout
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74
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75 * Byte receiver loop
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76 rxByte lda <$FF20 ; reset FIRQ
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77 sync ; wait for start bit
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78 leau ,u
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79 lda ,u ; bit 0
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80 lsra
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81 rolb
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82 lda ,u++ ; bit 1
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83 lsra
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84 rolb
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85 lda -2,u ; bit 2
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86 lsra
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87 rolb
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88 lda ,--u ; bit 3
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89 lsra
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90 rolb
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91 lda ,u++ ; bit 4
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92 lsra
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93 rolb
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94 lda ,--u ; bit 5
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95 lsra
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96 rolb
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97 lda ,u+ ; bit 6
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98 lsra
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99 rolb
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100 nop
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101 lda ,-u ; bit 7
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102 lsra
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103 rolb
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104 abx ; update checksum
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105 stb ,y+ ; put byte to storage
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106 decw ; decrement counter
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107 bne rxByte ; loop if more bytes to read
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108 clra ; status = SUCCESS
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109 rxDone sta 5,s ; store status on stack
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110
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111 * Restore previous PIA control settings
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112 puls d ; restore original PIA 1 controls
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113 sta <$FF21
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114 stb <$FF23
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115 puls d ; restore original PIA 0 controls
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116 sta <$FF01
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117 stb <$FF03
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118 lda <$FF20 ; make sure the CD FIRQ has been cleared
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119
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2602
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120 IFEQ NITROS9-1
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2576
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121 * Restoration of GIME interrupts in NitrOS9
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122 ldd >D.IRQER ; retrieve shadow copy of IRQ/FIRQ enable regs
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123 std <$FF92 ; restore GIME
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124 ldd <$FF92 ; clear spurious interrupts
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125 ENDIF
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126
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127 * Clean up and return
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128 leay ,x ; return checksum in Y
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129 puls cc,a,dp,u ; ACCA = status; restore IRQ masks, DP and U
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130 tsta ; set CC.Z if status = SUCCESS
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131 rts ; return
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132
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133 ELSE
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134
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2574
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135 *******************************************************
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136 *
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137 * DWRead - 6809 Turbo Edition 115k / 230k
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138 * Receive a response from the DriveWire server.
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139 * Times out if no data received within 1.3 (0.66) seconds.
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140 *
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141 * THIS VERSION REQUIRES ONE OR MORE SYNC BYTES
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142 * WHERE THE THE FINAL SYNC BYTE IS $C0 AND ANY
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143 * PRECEDING SYNC BYTES ARE $FF.
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144 *
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145 * THE DATA BYTES MUST BE TRANSMITTED IN REVERSE
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146 * BIT ORDER (MOST-SIGNIFICANT FIRST).
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147 *
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148 * Serial data format: 8-N-2 (TWO STOP BITS MANDATORY)
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149 *
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150 * Entry:
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151 * X = storage address for incoming data
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152 * Y = number of bytes required
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153 *
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154 * Exit:
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155 * CC = Z set on success, cleared on timeout
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156 * Y = checksum
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157 * U is preserved
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158 * All others clobbered
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159 *
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160 *BBIN equ $FF22 ; bit banger input port
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161 SETDP $FF
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162 DWRead pshs y,x,dp,a,cc ; save registers (A allocates space for status)
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163 orcc #$50 ; mask interrupts
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164 lda #$FF ; select hardware page..
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165 tfr a,dp ; ..as the direct page
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166 ldx #0 ; initialize timeout counter
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167 stx <$FF92 ; disable GIME interrupts
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168 ldd <$FF92 ; clear spurious interrupts
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169
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170 * Turn off PIA interrupt sources except for the bit banger's CD input pin.
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171 * Also enable sound output from the DAC to stabilize the single-bit sound line.
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172 lda <$FF01 ; save PIA 0 controls on the stack
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173 ldb <$FF03
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174 pshs d
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175 anda #$F6 ; clear IRQ enables and audio mux selects
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176 andb #$F6
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177 sta <$FF01 ; set new control state for PIA 0
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178 stb <$FF03
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179 lda <$FF00 ; ensure the IRQ outputs are cleared
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180 ldb <$FF02
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181 lda <$FF21 ; save PIA 1 controls on the stack
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182 ldb <$FF23
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183 pshs d,cc ; CC allocates space for byte adjustment value
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184 anda #$FC ; clear FIRQ enables and sound enable
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185 andb #$F6
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186 addd #$0108 ; set CD FIRQ enable and sound enable
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187 sta <$FF21 ; set new control state for PIA 1
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188 stb <$FF23
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189
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190 * Setup byte adjustment value
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191 ldd #$01FE ; ACCA = serial in mask; ACCB = byte adjust mask
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192 andb <BBIN ; ACCB = byte adjust value
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193 stb ,s ; save in pre-allocated stack space
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194
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195 * Wait for Sync Byte(s) or Timeout
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196 sync1 ldb #2 ; set counter to wait for 2 low samples
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197 sync2 bita <BBIN ; sample input
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198 beq sync3 ; branch if low
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199 leax ,-x ; decrement timeout counter
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200 bne sync1 ; loop if timeout has not expired
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201 bra rxDone ; exit due to timeout
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202 sync3 lsrb ; have there been 2 consecutive low samples?
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203 bcc sync2 ; keep waiting if no
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204 ldx 8,s ; point X to storage buffer and..
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205 leax -1,x ; ..adjust for pre-increment
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206 sync4 bita <BBIN ; sample input
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207 bne rxStart ; branch if input has returned hi
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208 rorb ; bump secondary timeout counter
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209 bcc sync4 ; branch if not timeout
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210 bra rxDone ; exit due to timeout
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211 rxStart lda <$FF20 ; reset FIRQ
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212 sync ; wait for the first byte's start bit
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213 jmp <rxFirst,pcr ; 4-cycle equivalent of: bra rxFirst
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214
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215 * Byte receiver loop
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216 rxNext sync ; wait for start bit
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217 sta ,x ; store previous data byte
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218 rxFirst lda <BBIN ; bit 0
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219 asla
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220 nop
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221 adda <BBIN ; bit 1
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222 asla
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223 adda >BBIN ; bit 2
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224 asla
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225 nop
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226 adda <BBIN ; bit 3
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227 asla
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228 clrb ; ACCB = 0
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229 adda <BBIN ; bit 4
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230 asla
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231 incb ; ACCB = 1
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232 adda <BBIN ; bit 5
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233 asla
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234 adda >BBIN ; bit 6
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235 asla
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236 abx ; increment storage ptr
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237 adda <BBIN ; bit 7
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238 adda ,s ; adjust byte value
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239 bita <$FF20 ; reset FIRQ
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240 leay -1,y ; decrement counter
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241 bne rxNext ; loop if more bytes to read
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242 sta ,x ; store final byte
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243 clra ; status = SUCCESS
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244 rxDone sta 6,s ; store status on stack
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245 leas 1,s ; pop byte adjustment value
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246
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247 * Restore previous PIA control settings
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248 puls d ; restore original PIA 1 controls
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249 sta <$FF21
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250 stb <$FF23
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251 puls d ; restore original PIA 0 controls
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252 sta <$FF01
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253 stb <$FF03
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254 lda <$FF20 ; make sure the CD FIRQ has been cleared
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255
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2602
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256 IFEQ NITROS9-1
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2574
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257 * Restoration of GIME interrupts in NitrOS9
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258 ldd >D.IRQER ; retrieve shadow copy of IRQ/FIRQ enable regs
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259 std <$FF92 ; restore GIME
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260 ldd <$FF92 ; clear spurious interrupts
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2576
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261 ENDIF
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2574
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262
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263 * Checksum computation
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264 clrb ; initialize checksum LSB
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265 puls cc,a,dp,x,y ; restore IRQ masks, DP and the caller params
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266 tsta ; timeout error?
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267 bne rxExit ; branch if yes
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268 sumLoop addb ,x+ ; get one byte and add to..
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269 adca #0 ; ..the 16-bit checksum in ACCD
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270 leay -1,y ; decrement counter
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271 bne sumLoop ; loop until all data summed
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272 andcc #$FE ; clear carry (no framing error)
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273 rxExit tfr d,y ; move checksum into Y without affecting CC.Z
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274 rts ; return
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2576
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275
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276 ENDC
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