Mercurial > hg > Members > kono > nitros9-code
annotate defs/dragon.d @ 3226:9749d0dfc4a2
Changed a puls PC to rts to save cycles
| author | David Ladd <drencor-xeen@users.sourceforge.net> |
|---|---|
| date | Sat, 20 Jan 2018 19:32:22 -0600 |
| parents | cbf1ad3c46b1 |
| children |
| rev | line source |
|---|---|
| 2624 | 1 IFNE DRAGON.D-1 |
| 2 DRAGON.D set 1 | |
| 3 | |
| 4 ******************************************************************** | |
| 5 * DgnDefs - Dragon I/O Definitions | |
| 6 * | |
| 7 * $Id$ | |
| 8 * | |
| 9 * Edt/Rev YYYY/MM/DD Modified by | |
| 10 * Comment | |
| 11 * ------------------------------------------------------------------ | |
| 12 * 2004/11/16 P.Harvey-Smith. | |
| 13 * Fixed the stupid error I made in the defines below that made all the | |
| 14 * non DPxxxxx defines equal to FF00 !!! | |
| 15 * | |
| 16 * 2005/04/14 P.Harvey-Smith | |
| 17 * Added non DP defines for ACIA on Dragon 64/Alpha | |
| 18 * | |
| 19 * 2005/04/21 P.Harvey-Smith | |
| 20 * Fixed errors in defines for WD2797 non-DP registers. | |
| 21 * | |
| 22 | |
| 23 nam DgnDefs | |
| 24 ttl Dragon I/O Definitions | |
| 25 | |
| 26 ************************************************* | |
| 27 * | |
| 28 * NitrOS-9 Level 1 Section | |
| 29 * | |
| 30 ************************************************* | |
| 31 | |
| 32 HW.Page SET $FF Device descriptor hardware page | |
| 33 | |
| 34 ********************************** | |
| 35 * Power Line Frequency Definitions | |
| 36 * | |
| 37 Hz50 EQU 1 Assemble clock for 50 hz power | |
| 38 Hz60 EQU 2 Assemble clock for 60 hz power | |
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39 IFNDEF PwrLnFrq |
| 2624 | 40 PwrLnFrq SET Hz60 Set to Appropriate freq |
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41 ENDC |
| 2624 | 42 |
| 43 | |
| 44 ********************************** | |
| 45 * Ticks per second | |
| 46 * | |
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47 IFNDEF TkPerSec |
| 2624 | 48 IFEQ PwrLnFrq-Hz50 |
| 49 TkPerSec SET 50 | |
| 50 ELSE | |
| 51 TkPerSec SET 60 | |
| 52 ENDC | |
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53 ENDC |
| 2624 | 54 |
| 55 | |
| 56 **************************************** | |
| 57 * Special character Bit position equates | |
| 58 * | |
| 59 SHIFTBIT EQU %00000001 | |
| 60 CNTRLBIT EQU %00000010 | |
| 61 ALTERBIT EQU %00000100 | |
| 62 UPBIT EQU %00001000 | |
| 63 DOWNBIT EQU %00010000 | |
| 64 LEFTBIT EQU %00100000 | |
| 65 RIGHTBIT EQU %01000000 | |
| 66 SPACEBIT EQU %10000000 | |
| 67 | |
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68 ****************** |
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69 * VDG Devices |
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70 * |
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71 A.TermV SET $FFC0 VDG Term |
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72 A.V1 SET $FFC1 Possible additional VDG Devices |
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73 A.V2 SET $FFC2 |
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74 A.V3 SET $FFC3 |
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75 A.V4 SET $FFC4 |
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76 A.V5 SET $FFC5 |
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77 A.V6 SET $FFC6 |
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78 A.V7 SET $FFC7 |
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79 |
| 2624 | 80 ******************** |
| 81 * VTIO Static Memory | |
| 82 * | |
| 83 * Definitions for ports on Dragon 32/64/Alpha. | |
| 84 * | |
| 85 * | |
| 86 IO equ $ff00 IO page on Dragon | |
| 87 | |
| 88 * | |
| 89 * Most of these symbols will be defined twice, as some | |
| 90 * of the Dragon code, sets DP=$FF, and uses direct page | |
| 91 * addressing to access the io ports, whilst some of it | |
| 92 * uses absolute addressing. | |
| 93 * The versions starting DP must be used with DP=$FF. | |
| 94 * | |
| 95 | |
| 96 * PIA 0 and 1 standard on all Dragons. | |
| 97 DPPIA0DA EQU $00 Side A Data/DDR | |
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98 PIA0Base EQU DPPIA0DA+IO |
| 2624 | 99 DPPIA0CRA EQU $01 Side A Control. |
| 100 DPPIA0DB EQU $02 Side B Data/DDR | |
| 101 DPPIA0CRB EQU $03 Side B Control. | |
| 102 | |
| 103 PIA0DA EQU DPPIA0DA+IO Side A Data/DDR | |
| 104 PIA0CRA EQU DPPIA0CRA+IO Side A Control. | |
| 105 PIA0DB EQU DPPIA0DB+IO Side A Data/DDR | |
| 106 PIA0CRB EQU DPPIA0CRB+IO Side A Control. | |
| 107 | |
| 108 DPPIA1DA EQU $20 Side A Data/DDR | |
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109 PIA1Base EQU DPPIA1DA+IO |
| 2624 | 110 DPPIA1CRA EQU $21 Side A Control. |
| 111 DPPIA1DB EQU $22 Side B Data/DDR | |
| 112 DPPIA1CRB EQU $23 Side B Control. | |
| 113 | |
| 114 PIA1DA EQU DPPIA1DA+IO Side A Data/DDR | |
| 115 PIA1CRA EQU DPPIA1CRA+IO Side A Control. | |
| 116 PIA1DB EQU DPPIA1DB+IO Side A Data/DDR | |
| 117 PIA1CRB EQU DPPIA1CRB+IO Side A Control. | |
| 118 | |
| 119 * Dragon Alpha has a third PIA at $FF24. | |
| 120 DPPIA2DA EQU $24 Side A Data/DDR | |
| 121 DPPIA2CRA EQU $25 Side A Control. | |
| 122 DPPIA2DB EQU $26 Side B Data/DDR | |
| 123 DPPIA2CRB EQU $27 Side B Control. | |
| 124 | |
| 125 PIA2DA EQU DPPIA2DA+IO Side A Data/DDR | |
| 126 PIA2CRA EQU DPPIA2CRA+IO Side A Control. | |
| 127 PIA2DB EQU DPPIA2DB+IO Side A Data/DDR | |
| 128 PIA2CRB EQU DPPIA2CRB+IO Side A Control. | |
| 129 | |
| 130 * WD2797 Floppy disk controler, used in Alpha Note registers in reverse order ! | |
| 131 DPCmdRegA EQU $2F command/status | |
| 132 DPTrkRegA EQU $2E Track register | |
| 133 DPSecRegA EQU $2D Sector register | |
| 134 DPDataRegA EQU $2C Data register | |
| 135 | |
| 136 CmdRegA EQU DPCMDREGA+IO command/status | |
| 137 TrkRegA EQU DPTRKREGA+IO Track register | |
| 138 SecRegA EQU DPSECREGA+IO Sector register | |
| 139 DataRegA EQU DPDATAREGA+IO Data register | |
| 140 | |
| 2670 | 141 DPort SET DataRegA Disk controller base address |
| 2624 | 142 |
| 143 * Constants for Alpha AY-8912 sound chip, which is used to control | |
| 144 * Drive select and motor on the Alpha | |
| 145 AYIOREG EQU $0E AY-8912, IO Register number. | |
| 146 AYIdle EQU $00 Make AY Idle. | |
| 147 AYWriteReg EQU $01 Write AY Register | |
| 148 AYReadReg EQU $02 Read AY Register | |
| 149 AYREGLatch EQU $03 Latch register into AY | |
| 150 | |
| 151 DSMask EQU $03 Drive select mask. | |
| 152 MotorMask EQU $04 Motor enable mask | |
| 153 DDENMask EQU $08 DDEN Mask | |
| 154 ENPMask EQU $10 Enable Precomp mask | |
| 155 NMIMask EQU $20 NMI enable Mask | |
| 156 | |
| 157 * Dragon 64/Alpha Serial port. | |
| 158 DPAciaData EQU $04 ACIA Rx/Tx Register | |
| 159 DPAciaStat EQU $05 ACIA status register | |
| 160 DPAciaCmd EQU $06 ACIA command register | |
| 161 DPAciaCtrl EQU $07 ACIA control register | |
| 162 | |
| 163 AciaData EQU DPAciaData+IO ACIA Rx/Tx Register | |
| 164 AciaStat EQU DPAciaStat+IO ACIA status register | |
| 165 AciaCmd EQU DPAciaCmd+IO ACIA command register | |
| 166 AciaCtrl EQU DPAciaCtrl+IO ACIA control register | |
| 167 | |
| 168 * DragonDos Cartrage IO for WD2797 | |
| 169 * WD2797 Floppy disk controler, used in DragonDos. | |
| 170 DPCmdRegD EQU $40 command/status | |
| 171 DPTrkRegD EQU $41 Track register | |
| 172 DPSecRegD EQU $42 Sector register | |
| 173 DPDataRegD EQU $43 Data register | |
| 174 | |
| 175 CmdRegD EQU DPCMDREGD+IO command/status | |
| 176 TrkRegD EQU DPTRKREGD+IO Track register | |
| 177 SecRegD EQU DPSECREGD+IO Sector register | |
| 178 DataRegD EQU DPDATAREGD+IO Data register | |
| 179 | |
| 180 DPDSKCTL EQU $48 Disk DS/motor control reg | |
| 181 DSKCTL EQU DPDSKCTL+IO | |
| 182 | |
| 183 * Disk IO bitmasks (DragonDos). | |
| 184 NMIEnD EQU %00100000 | |
| 185 WPCEnD EQU %00010000 | |
| 186 SDensEnD EQU %00001000 | |
| 187 MotorOnD EQU %00000100 | |
| 188 Drive0D EQU %00000000 | |
| 189 Drive1D EQU %00000001 | |
| 190 Drive2D EQU %00000010 | |
| 191 Drive3D EQU %00000011 | |
| 192 DDosDriveMask EQU %00000011 Mask out all non drive select bits | |
| 193 DDosCtrlMask EQU %11111100 Mask in all non drive select bits | |
| 194 | |
| 195 | |
| 196 * Disk IO bitmasks (Dragon Alpha). | |
| 197 PIANMIEnA EQU %00001000 PIA2, CA2, used to enable/disable NMI | |
| 198 PIANMIDisA EQU %11110111 Bitmask to force CA2 off, and disable NMI | |
| 199 | |
| 200 NMIEnA EQU %10000000 Flag to enable disable NMI, passed to AlphaDskCtl | |
| 201 WPCEnA EQU %01000000 According to circuit trace by R.Harding. | |
| 202 SDensEnA EQU %00100000 DDen, from circuit trace on R.Harding's machine. | |
| 203 MotorOnA EQU %00010000 | |
| 204 Drive0A EQU %00000001 | |
| 205 Drive1A EQU %00000010 | |
| 206 Drive2A EQU %00000100 | |
| 207 Drive3A EQU %00001000 | |
| 208 AlphaDrvMask EQU %00001111 Mask out all non drive select bits | |
| 209 AlphaCtrlMask EQU %11110000 Mask in all non drive select bits | |
| 210 | |
| 211 Mask58 EQU %01111111 And mask to make sure 5.25" clock selected by WD2797 | |
| 212 | |
| 213 NMICA2En EQU $3C Value for PIA CRA to enable NMI | |
| 214 NMICA2Dis EQU $34 Value for PIA CRA to disable NMI | |
| 215 | |
| 216 * Disk Commands | |
| 217 FrcInt EQU %11010000 | |
| 218 ReadCmnd EQU %10001000 | |
| 219 RestCmnd EQU %00000000 | |
| 220 SeekCmnd EQU %00010000 | |
| 221 StpICmnd EQU %01000000 | |
| 222 WritCmnd EQU %10101000 | |
| 223 WtTkCmnd EQU %11110000 | |
| 224 Sid2Sel EQU %00000010 | |
| 225 | |
| 226 * Disk Status Bits | |
| 227 BusyMask EQU %00000001 | |
| 228 LostMask EQU %00000100 | |
| 229 ErrMask EQU %11111000 | |
| 230 CRCMask EQU %00001000 | |
| 231 RNFMask EQU %00010000 | |
| 232 RTypMask EQU %00100000 | |
| 233 WPMask EQU %01000000 | |
| 234 NotRMask EQU %10000000 | |
| 235 | |
| 236 DensMask EQU %00000001 | |
| 237 T80Mask EQU %00000010 | |
| 238 | |
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239 ******************************** |
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240 * Boot defs for NitrOS-9 Level 1 |
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241 * |
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242 * These defs are not strictly for 'Boot', but are for booting the |
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243 * system. |
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244 * |
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245 * Boot area size on Dragon is only 16 sectors=4K |
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246 Bt.Size EQU $1000 Max size of boot file |
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247 * Boot area on the Dragon starts on track 0 sector 2, immediately |
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248 * after the blockmap. |
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249 Bt.Track EQU 0 Boot track |
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250 Bt.Sec EQU 2 Start LSN of boot area on boot track |
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251 Bt.Start EQU $EE00 Start address of the boot track in memory |
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252 |
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253 ENDC |