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annotate level2/mc09l2/port.mak @ 3226:9749d0dfc4a2

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Changed a puls PC to rts to save cycles
author David Ladd <drencor-xeen@users.sourceforge.net>
date Sat, 20 Jan 2018 19:32:22 -0600
parents e1aadba01e81
children
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3131
e1aadba01e81 Add new Level 2 port for Multicomp09 "mc09l2"
Neal Crook <foofoobedoo@gmail.com>
parents:
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1 PORT = mc09
e1aadba01e81 Add new Level 2 port for Multicomp09 "mc09l2"
Neal Crook <foofoobedoo@gmail.com>
parents:
diff changeset
2 MACHINE = Multicomp09 FPGA-based Computer
e1aadba01e81 Add new Level 2 port for Multicomp09 "mc09l2"
Neal Crook <foofoobedoo@gmail.com>
parents:
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3 CPU = 6809
e1aadba01e81 Add new Level 2 port for Multicomp09 "mc09l2"
Neal Crook <foofoobedoo@gmail.com>
parents:
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4 LEVEL = 2
e1aadba01e81 Add new Level 2 port for Multicomp09 "mc09l2"
Neal Crook <foofoobedoo@gmail.com>
parents:
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5 TELNET_PORT = 6809
e1aadba01e81 Add new Level 2 port for Multicomp09 "mc09l2"
Neal Crook <foofoobedoo@gmail.com>
parents:
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6 HTTPD_PORT = 8809
e1aadba01e81 Add new Level 2 port for Multicomp09 "mc09l2"
Neal Crook <foofoobedoo@gmail.com>
parents:
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7
e1aadba01e81 Add new Level 2 port for Multicomp09 "mc09l2"
Neal Crook <foofoobedoo@gmail.com>
parents:
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8 include $(NITROS9DIR)/rules.mak
e1aadba01e81 Add new Level 2 port for Multicomp09 "mc09l2"
Neal Crook <foofoobedoo@gmail.com>
parents:
diff changeset
9