annotate level2/modules/clock2_146818.asm @ 91:c10820aa211b

Added
author boisy
date Wed, 03 Jul 2002 03:41:59 +0000
parents 6641a883d6b0
children 02a8ba2b9092
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
1 ********************************************************************
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
2 * Clock2 - Motorola 146818 clock driver
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
3 *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
4 * $Id$
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
5 *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
6 * Ed. Comments Who YY/MM/DD
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
7 * ------------------------------------------------------------------
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
8 * 1 Created BRI 88/10/06
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
9 * 2 Shift D.Tick & exit if UIP (not wait up to
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
10 * 2228 uS for completion), general clean up BRI 88/11/17
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
11 * 3 Re-wrote clock access to eliminate repeated
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
12 * subroutine calls to increase speed BRI 88/11/26
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
13 * 4 Changed clock access to once per minute BRI 89/03/25
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
14 * 5 More changes BRI 90/04/15
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
15
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
16 nam Clock2
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
17 ttl Motorola 146818 clock driver
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
18
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
19 edition equ 5
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
20 MPISlot equ $33 (MPI Slot $00-$33)
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
21
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
22 ifp1
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
23 use defsfile
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
24 endc
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
25
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
26 ClkAddr equ $FF72 clock base address
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
27 Vrsn equ 1
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
28 SpeedClk equ $20 32.768 KHz, rate=0
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
29 StartClk equ $06 binary, 24 Hour, DST disabled
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
30 StopClk equ $86 bit 7 set stops clock to allow setting t
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
31
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
32 * MC146818/DS1287 clock register map:
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
33 org $00
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
34 CRegSec rmb $01 seconds register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
35 CRegSAl rmb $01 seconds alarm register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
36 CRegMin rmb $01 minutes register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
37 CRegMAl rmb $01 minutes alarm register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
38 CRegHour rmb $01 hours register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
39 CRegHAl rmb $01 hours alarm register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
40 CRegDayW rmb $01 day of week register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
41 CRegDayM rmb $01 day of month register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
42 CRegMnth rmb $01 months register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
43 CRegYear rmb $01 years register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
44 CRegA rmb $01 bits 7-0: UIP (read only); DV2-DV0; RS3-
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
45 CRegB rmb $01 bits 7-0: SET; PIE; AIE; UIE; SQWE; DM;
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
46 CRegC rmb $01 bits 7-0: IRQF; PF; AF; UF; Unused3-Unus
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
47 CRegD rmb $01 bits 7-0: VRT; Unused6-Unused0
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
48 CSRAM rmb $40-. CMOS static RAM
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
49
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
50 mod CSize,CNam,Systm+Objct,ReEnt+Vrsn,Entry,ClkAddr
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
51
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
52 CNam fcs "Clock2"
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
53 fcb edition
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
54 *RTCSlot fcb MPISlot
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
55
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
56 Entry bra Init clock hardware initialization gets time
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
57 nop maintain 3 byte entry table spacing
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
58 bra GetTime get hardware time
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
59 nop save a couple cycles with short branch a
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
60 SetTime clrb no error for return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
61 pshs cc,d,x,y,u save regs which will be altered
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
62 ldx <M$Mem,pcr get clock base addr
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
63 leay <SetTable,pcr point [Y] to RTC register set table
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
64 ldu #D.Time point [U] to time variables in DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
65 ldb #(SetEnd-SetTable)/2 get loop count
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
66 stb R$B,s save counter to B reg on stack
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
67 orcc #IntMasks disable IRQs while setting clock
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
68 CSetLoop ldd ,y++ get clock set data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
69 bmi CRegSet [A] Sign bit set, go save [B] to clock requirement
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
70 ldb b,u get system time from D.Time variables
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
71 CRegSet anda #^Sign clear sign bit
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
72 std ,x generate clock address strobe, store dat
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
73 dec R$B,s done all clock regs?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
74 bne CSetLoop no, go do next...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
75 L003A ldb #$01
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
76 stb <$002E
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
77 puls cc,d,x,y,u,pc restore altered regs, return to caller
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
78
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
79 SetTable equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
80 fcb Sign+CRegB,StopClk
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
81 fcb Sign+CRegA,SpeedClk
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
82 GetTable equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
83 fcb CRegYear,D.Year-D.Time
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
84 fcb CRegMnth,D.Month-D.Time
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
85 fcb CRegDayM,D.Day-D.Time
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
86 fcb CRegHour,D.Hour-D.Time
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
87 fcb CRegMin,D.Min-D.Time
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
88 fcb CRegSec,D.Sec-D.Time
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
89 GetEnd equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
90 fcb Sign+CRegDayW,$01
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
91 fcb Sign+CRegHAl,$00
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
92 fcb Sign+CRegMAl,$00
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
93 fcb Sign+CRegSAl,$00
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
94 fcb Sign+CRegB,StartClk
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
95 SetEnd equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
96
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
97 Init ldb #59 last second in minute
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
98 stb <D.Sec force RTC read
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
99
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
100 GetTime clrb no error for return...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
101 pshs cc,d,x,y,u save regs which will be altered
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
102 ldb <D.Sec get current second
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
103 incb next...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
104 cmpb #60 done minute?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
105 bhs CGetT00 yes, go read RTC...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
106 stb <D.Sec set new second
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
107 bra CGExit go clean up & return
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
108 CGetT00 ldx <M$Mem,pcr get clock base addr
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
109 lda #CRegA RTC Update In Progress status register
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
110 sta ,x generate address strobe
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
111 lda 1,x get UIP status
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
112 bmi L003A RTC Update In Progress (1:449 chance), go shft D.Ticki
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
113 leay <GetTable,pcr point [Y] to RTC "get" register info table
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
114 ldu #D.Time point [U] to time variables in DP
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
115 ldb #$06
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
116 stb R$B,s save counter to B reg on stack
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
117 CGetLoop ldd ,y++ get clock register info from table
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
118 sta ,x generate clock address strobe
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
119 lda 1,x get clock data
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
120 sta b,u save data to D.Time variables
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
121 dec R$B,s done all D.Time vars?
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
122 bne CGetLoop no, go do next...
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
123 CGExit puls cc,d,x,y,u,pc recover regs, return to caller
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
124
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
125 emod
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
126 CSize equ *
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
127 end
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
128
6641a883d6b0 Initial revision
boisy
parents:
diff changeset
129