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annotate defs/mc09.d @ 3162:c44cd20907bd

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author Neal Crook <foofoobedoo@gmail.com>
date Thu, 06 Apr 2017 22:04:46 +0100
parents 927ba5ebc06e
children cbf1ad3c46b1
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1 IFNE MC09.D-1
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2 MC09.D SET 1
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3
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4 ********************************************************************
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5 * mc09.d - NitrOS-9 System Definitions for the Multicomp09
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6 *
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7 * When the primary boot loader passes control to the "track34" code
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8 * the system memory map looks like this:
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9 *
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10 * $0000----> ==================================
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11 * | |
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12 * | |
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13 * | RAM |
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14 * | |
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15 * | |
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16 * $FFD0---->|==================================|
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17 * | I/O |
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18 * $FFE0---->|==================================|
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19 * | RAM |
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20 * |==================================|
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21 * $FFFF---->
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22 *
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23 * The exception vectors at $FFF2 and onwards are initialised to vector to RAM
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24 * as per coco1, just as krn expects. Specifically:
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25 *
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26 * $FFF2 holds vector to $0100 for SWI3
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27 * $FFF4 holds vector to $0103 for SWI2
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28 * $FFF6 holds vector to $010F for FIRQ
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29 * $FFF8 holds vector to $010C for IRQ
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30 * $FFFA holds vector to $0106 for SWI
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31 * $FFFC holds vector to $0109 for NMI
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32 *
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33 * The 16-location I/O space and the interrupt hook-up are described below.
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34 *
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35 * $Id$
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36 *
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37 * Edt/Rev YYYY/MM/DD Modified by
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38 * Comment
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39 * ------------------------------------------------------------------
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40 * 0.1 2015/10/17 Neal Crook. Tidy-up for first commit.
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41 *
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42 NAM Multicomp09Defs
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43 IFEQ Level-1
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44 TTL NitrOS-9 System Definitions for the Multicomp09
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45 ELSE
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46 IFEQ Level-2
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47 TTL NitrOS-9 Level 2 System Type Definitions
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48 ELSE
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49 IFEQ Level-3
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50 TTL NitrOS-9 Level 3 System Type Definitions
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51 ENDC
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52 ENDC
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53 ENDC
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54
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55
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56 **********************
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57 * CPU Type Definitions
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58 *
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59 Color SET 1
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60 Color3 SET 2
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61 IFEQ Level-1
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62 CPUType SET Color
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63 ELSE
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64 CPUType SET Color3
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65 ENDC
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66
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67
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68 ******************************
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69 * Clock Speed Type Definitions
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70 *
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71 OneMHz EQU 1
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72 TwoMHz EQU 2
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73 IFEQ CPUType-Color
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74 CPUSpeed SET OneMHz
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75 ELSE
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76 CPUSpeed SET TwoMHz
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77 ENDC
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78
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79
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80 **********************************
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81 * Power Line Frequency Definitions
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82 * Multicomp09 has no dependency on power line frequency but setting
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83 * it to Hz50 is the simplest way to make TkPerSec 50, which is important
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84 * [NAC HACK 2015Aug31] actually no need to change it - gets applied at
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85 * command line in modules/makefile to generate a 50Hz and 60Hz version.
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86 *
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87 Hz50 EQU 50 Assemble clock for 50 hz power
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88 Hz60 EQU 60 Assemble clock for 60 hz power
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89 IFNDEF PwrLnFrq
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90 PwrLnFrq SET Hz50 Set to Appropriate freq
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91 ENDC
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92
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93
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94 **********************************
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95 * Ticks per second
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96 *
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97 IFNDEF TkPerSec
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98 IFEQ PwrLnFrq-Hz50
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99 TkPerSec SET 50
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100 ELSE
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101 TkPerSec SET 60
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102 ENDC
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103 ENDC
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104
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105
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106 ******************
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107 * ACIA type set up
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108 *
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109 * [NAC HACK 2015Sep06] is this used anywhere?
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110 ORG 1
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111 ACIA6850 RMB 1 MC6850 acia.
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112 ACIA6551 RMB 1 SY6551 acia.
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113 ACIA2661 RMB 1 SC2661 acia.
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114 ACIATYPE SET ACIA6551
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115
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116
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117 ****************************************
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118 * Special character Bit position equates
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119 *
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120 SHIFTBIT EQU %00000001
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121 CNTRLBIT EQU %00000010
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122 ALTERBIT EQU %00000100
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123 UPBIT EQU %00001000
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124 DOWNBIT EQU %00010000
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125 LEFTBIT EQU %00100000
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126 RIGHTBIT EQU %01000000
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127 SPACEBIT EQU %10000000
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128
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129
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130 ********************************************************************
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131 * Multicomp09 Interrupts:
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132 *
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133 * NMI - wired to single-step logic
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134 * FIRQ - (currently) unused
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135 * IRQ - wired to timer interrupt, VDU/KBD virtual ACIA and serial
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136 * ports 1 and 2.
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137
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138 ********************************************************************
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139 * Multicomp09 I/O space is $FFD0-$FFDF (16 locations). The equates
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140 * below describe the I/O registers.
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141
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142 ********************************************************************
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143 * VDU/KBD (VIRTUAL ACIA)
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144 VDUSTA EQU $FFD0
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145 VDUDAT EQU $FFD1
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146
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147 * SERIAL PORT 1
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148 UARTSTA1 EQU $FFD2
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149 UARTDAT1 EQU $FFD3
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150
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151 * SERIAL PORT 2
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152 UARTSTA2 EQU $FFD4
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153 UARTDAT2 EQU $FFD5
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154
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155 ********************************************************************
3116
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156 * GPIO device
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157 * SEE VHDL HEADER FOR PROG GUIDE
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158 GPIOADR EQU $FFD6
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159 GPIODAT EQU $FFD7
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160
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161 * values supported by GPIOADR register
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162 GPDAT0 EQU 0
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163 GPDDR1 EQU 1
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164 GPDAT2 EQU 2
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165 GPDDR3 EQU 3
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166
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167
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168 ********************************************************************
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169 * SDCARD CONTROL REGISTERS
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170 * SEE VHDL HEADER FOR PROG GUIDE
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171 SDDATA EQU $FFD8
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172 SDCTL EQU $FFD9
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173 SDLBA0 EQU $FFDA
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174 SDLBA1 EQU $FFDB
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175 SDLBA2 EQU $FFDC
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176
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177 ********************************************************************
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178 * 50Hz TIMER INTERRUPT
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179 * TIMER (READ/WRITE)
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180 *
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181 * AT RESET, THE TIMER IS DISABLED AND THE INTERRUPT IS DEASSERTED. TIMER READS AS 0.
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182 * BIT[1] IS READ/WRITE, TIMER ENABLE.
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183 * BIT[7] IS READ/WRITE-1-TO-CLEAR, INTERRUPT.
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184 *
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185 * IN AN ISR THE TIMER CAN BE SERVICED BY PERFORMING AN INC ON ITS ADDRESS
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186 *
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187 * READ WRITE COMMENT
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188 * N/A $02 ENABLE TIMER
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189 * $00 $01 TIMER WAS/REMAINS DISABLED. N=0.
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190 * $02 $03 TIMER WAS/REMAINS ENABLED, NO INTERRUPT. N=0.
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191 * $80 $81 TIMER WAS/REMAINS DISABLED, OLD PENDING INTERRUPT CLEARED. N=1.
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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192 * $82 $83 TIMER WAS/REMAINS DISABLED, OLD PENDING INTERRUPT CLEARED. N=1.
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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193 *
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194 TIMER EQU $FFDD
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195
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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196 ********************************************************************
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197 * MEM_MAPPER2 CONTROL REGISTERS
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198 * MMUADR (WRITE-ONLY)
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199 * 7 - ROMDIS (RESET TO 0)
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200 * 6 - TR
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201 * 5 - MMUEN (RESET TO 0)
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202 * 4 - NMI
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203 * 3:0 - MAPSEL
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204 *
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205 * MMUDAT (WRITE-ONLY)
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206 * 7 - WRPROT
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207 * 6:0 - PHYSICAL BLOCK FOR CURRENT MAPSEL
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208 *
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209 *
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210 * Magic: for NitrosL2, want a fixed 512byte region of r/w memory
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211 * at the top of the address space. There is no space to provide
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212 * an enable for this behaviour (which I call FRT for FixedRamTop)
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213 * and so some special magic is used, as follows:
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214 *
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215 * IF ROMDIS=1 & MMUEN=1 then a write with b4=0 (see NMI behaviour
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216 * below) and b7=0 and b5=1 does NOT enable the ROM but actually
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217 * sets FRT=1. Any write with MMUEN=0 sets FRT=0 again. In summary:
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218 *
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219 * Current Action End State
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220 * -----------------+-------------+-----------------
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221 * ROMDIS MMUEn FRT ROMDIS MMUEn ROMDIS MMUEn FRT
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222 * x x x RESET 0 0 0
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223 * x x x 0 1 0 1 x
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224 * x x x 1 1 1 1 x
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225 * x x x x 0 x 0 0
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226 * 1 1 x 0 1 1 1 1
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227
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228 MMUADR EQU $FFDE
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229 MMUDAT EQU $FFDF
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230
3158
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231 * BIT-FIELDS
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232 MMUADR_ROMDIS EQU $80 0 after reset, 1 when OS boots. Leave at 1.
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233 MMUADR_TR EQU $40 0 after reset, 0 when OS boots. 0=user, 1=sys
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234 MMUADR_MMUEN EQU $20 0 after reset, 1 when OS boots. Leave at 1.
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235 MMUADR_NMI EQU $10 0 after reset, 0 when OS boots. Do not write 1.
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236 MMUADR_MAPSEL EQU $0f last-written value is UNDEFINED.
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237 * the only two useful values for the upper nibble
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238 MMU_TR0 EQU (MMUADR_ROMDIS|MMUADR_MMUEN)
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239 MMU_TR1 EQU (MMUADR_ROMDIS|MMUADR_MMUEN|MMUADR_TR)
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240 * one-time write to enable FRT
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parents: 3118
diff changeset
241 MMU_TR0FRT EQU (MMUADR_MMUEN)
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parents: 3118
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242 MMU_TR1FRT EQU (MMUADR_MMUEN|MMUADR_TR)
3116
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243
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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244
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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245 ********************************************************************
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
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246 ********************************************************************
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
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247 * Coco stuff that's needed to allow other files to compile
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parents:
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248 * [NAC HACK 2015Oct17] need to get rid of this eventually.
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249
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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250 A.AciaP SET $FF68 Aciapak Address
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251 A.ModP SET $FF6C ModPak Address
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252 DPort SET $FF40 Disk controller base address
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253 MPI.Slct SET $FF7F Multi-Pak slot select
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254 MPI.Slot SET $03 Multi-Pak default slot
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parents:
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255 PIA0Base EQU $FF00
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parents:
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256 PIA1Base EQU $FF20
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257
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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258
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259 ******************
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
260 * VDG Devices
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
261 *
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
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262 A.TermV SET $FFC0 VDG Term
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
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263 A.V1 SET $FFC1 Possible additional VDG Devices
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parents:
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264 A.V2 SET $FFC2
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
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265 A.V3 SET $FFC3
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parents:
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266 A.V4 SET $FFC4
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267 A.V5 SET $FFC5
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268 A.V6 SET $FFC6
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269 A.V7 SET $FFC7
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270
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271
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272 IFEQ Level-1
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273
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274 *************************************************
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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275 *
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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276 * NitrOS-9 Level 1 Section
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277 *
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
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278 *************************************************
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279
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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280 HW.Page SET $FF Device descriptor hardware page
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281
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282 ELSE
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283
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parents:
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284 *************************************************
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
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285 *
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
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286 * NitrOS-9 Level 2 Section
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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287 *
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288 *************************************************
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289
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290 ****************************************
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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291 * Dynamic Address Translator Definitions
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292 *
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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293 DAT.BlCt EQU 8 D.A.T. blocks/address space
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294 DAT.BlSz EQU (256/DAT.BlCt)*256 D.A.T. block size
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parents:
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295 DAT.ImSz EQU DAT.BlCt*2 D.A.T. Image size
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parents:
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296 DAT.Addr EQU -(DAT.BlSz/256) D.A.T. MSB Address bits
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297 DAT.Task EQU $FF91 Task Register address
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parents:
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298 DAT.TkCt EQU 32 Number of DAT Tasks
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parents:
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299 DAT.Regs EQU $FFA0 DAT Block Registers base address
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
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300 DAT.Free EQU $333E Free Block Number
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parents:
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301 DAT.BlMx EQU $3F Maximum Block number
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parents:
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302 DAT.BMSz EQU $40 Memory Block Map size
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parents:
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303 DAT.WrPr EQU 0 no write protect
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parents:
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304 DAT.WrEn EQU 0 no write enable
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parents:
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305 SysTask EQU 0 Coco System Task number
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
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306 IOBlock EQU $3F
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
307 ROMBlock EQU $3F
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
308 IOAddr EQU $7F
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diff changeset
309 ROMCount EQU 1 number of blocks of ROM (High RAM Block)
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310 RAMCount EQU 1 initial blocks of RAM
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parents:
diff changeset
311 MoveBlks EQU DAT.BlCt-ROMCount-2 Block numbers used for copies
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parents:
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312 BlockTyp EQU 1 chk only first bytes of RAM block
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parents:
diff changeset
313 ByteType EQU 2 chk entire block of RAM
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parents:
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314 Limited EQU 1 chk only upper memory for ROM modules
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parents:
diff changeset
315 UnLimitd EQU 2 chk all NotRAM for modules
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parents:
diff changeset
316 * NOTE: this check assumes any NotRAM with a module will
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
317 * always start with $87CD in first two bytes of block
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parents:
diff changeset
318 RAMCheck EQU BlockTyp chk only beg bytes of block
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parents:
diff changeset
319 ROMCheck EQU Limited chk only upper few blocks for ROM
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parents:
diff changeset
320 LastRAM EQU IOBlock maximum RAM block number
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parents:
diff changeset
321
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
322 ***************************
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
323 * Color Computer 3 Specific
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
324 *
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
325 MappedIO EQU true (Actually False but it works better this way)
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
326
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
327 ********************
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
328 * Hardware addresses
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
329 *
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
330 GIMERegs EQU $FF00 Base address of GIME registers
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
331 IrqEnR EQU $FF92 GIME IRQ enable/status register
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
332 BordReg EQU $FF9A Border color register
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
333 PalAdr EQU $FFB0 Palette registers
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
334
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
335 HW.Page SET $07 Device descriptor hardware page
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
336
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
337 ENDC
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
338
174eb9eda7b1 New port "mc09" for Multicomp09, an FPGA-based 6809 machine
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parents:
diff changeset
339 ENDC