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annotate level1/modules/rb1773.asm @ 1631:ec6fb5543b22

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Robert Gault's modifications for correcting timing errors
author boisy
date Mon, 12 Jul 2004 01:38:08 +0000
parents c228f9fbe3b8
children 93d5b9ff0f4a
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1 ********************************************************************
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2 * rb1773 - Western Digital 1773 Disk Controller Driver
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3 *
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4 * $Id$
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5 *
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6 * This driver has been tested with the following controllers:
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7 * - Tandy FD-502 "shortie" disk controller
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8 * - Disto Super Controller I
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9 * - Disto Super Controller II
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10 *
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11 * This driver can also be assembled to support the no-halt feature of
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12 * the Disto Super Controller II.
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13 *
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14 *
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15 * A lot of references to **.CYL or <u00B6 using 16 bit registers can be
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16 * changed to 8 bit registers with a +1 offset, since track #'s >255 are
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17 * ignored
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18 *
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19 * NOTE: 512 bytes is reserved as a physical sector buffer. Any reads/
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20 * writes are done from this buffer to the controller. Copies of the 256
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21 * byte chunk needed are done by a block memory move
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22 *
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23 *
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24 ********** DISTO SUPER CONTROLLER II NOTES **********
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25 *
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26 * SCII 0=standard controller 1=Disto Super Controller II
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27 * SCIIALT 0=Normal I/O register 1=Alternative registers; See below
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28 *
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29 * Disto Super Controller II Registers:
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30 *
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31 * $FF74 RW.Dat --- R/W Buffer data #1
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32 * $FF75 mirror of $FF74
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33 * $FF76 RW.Ctrl --- Write D0 = 0 FDC Write Op #2
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34 * = 1 FDC Read Op #2
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35 * D1 = 0 Normal Mode
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36 * = 1 Buffered I/O Mode
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37 * D2 = 0 Normal NMI
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38 * = 1 Masked NMI
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39 * D3 = 0 No FIRQ (Masked)
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40 * = 1 Enabled FIRQ
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41 * Read D7 = FDC INT Status (Inverted)
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42 * $FF77 mirror of $FF76
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43 * #1: any write to $FF76-$FF77 clears Buffer counter
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44 * #2: in buffered mode only
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45 *
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46 * Alternate port is at $FF58-$FF5B in case of hardware conflicts.
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47 *
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48 * Edt/Rev YYYY/MM/DD Modified by
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49 * Comment
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50 * ------------------------------------------------------------------
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51 * 11 1993/05/12 ???
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52 * Special opts for TC9 to slow controller reads and writes TFM's
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53 * between sector buffers & in drive table init/copies.
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54 * Changed software timing loop (drive spin-up) to F$Sleep for 32 ticks
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55 * Shrunk (slowed slightly) error returns
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56 * Added blobstop code
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57 *
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58 * 11r1 2003/09/03 Boisy G. Pitre
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59 * Added code to sense if HW is present or not and return error if not.
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60 *
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61 * 1r0 2004/05/20 Boisy G. Pitre
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62 * Restarted edition due to name change; backported to Level 1
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63 *
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64 * 2004/06/01 Robert Gault
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65 * Added code to obtain an SCII driver, at least for the Sleep mode. It
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66 * would be quite difficult and probably not worth the effort to permit
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67 * selection of both Sleep and IRQ SCII drivers. However, both normal
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68 * and Alt SCII I/O registers are supported.
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69 *
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70 * Cleaned up some errors in the last version of rb1773.
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71 *
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72 * 2004/07/11 Robert Gault
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73 * Corrected the error handling code for read & write to separate SCII errors
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74 * from OS-9 errors. Changed drive test from compare #4 to compare #N.Drives to
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75 * permit up to 6 drives using alternate table.
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76
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77 nam rb1773
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78 ttl Western Digital 1773 Disk Controller Driver
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79
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80 * These lines needed if assembling with on a Color computer.
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81 *SCII set 1 * 0=not present 1=present
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82 *SCIIALT set 1 * 0=normal address 1=alternate
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83 SCIIHACK set 0 * 0=stock model 1=512 byte buffer
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84 *H6309 set 1
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85 *LEVEL set 2
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86 * These lines needed if not using latest os9def files.
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87 *TkPerSec set 60
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88 *DPort set $FF40
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89
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90 * This should be changed for NitrOS9 project to "use defsfile"
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91 IFP1
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92 use defsfile
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93 ENDC
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94
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95 tylg set Drivr+Objct
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96 atrv set ReEnt+rev
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97 rev set $00
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98 edition set 1
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99
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100 * Configuration Settings
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101 N.Drives equ 4 number of drives to support
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102 TC9 equ 0 Set to 1 for TC9 special slowdowns
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103 PRECOMP equ 0 Set to 1 to turn on write precompensation
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104
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105 * Disto Super Controller defs
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106 IFEQ SCIIALT
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107 RW.Dat equ $FF74
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108 RW.Ctrl equ $FF76
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109 ELSE
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110 RW.Dat equ $FF58
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111 RW.Ctrl equ $FF5A
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112 ENDC
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113
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114
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115 * WD-17X3 Definitions
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116 CtrlReg equ $00 Control register for Tandy controllers; not part of WD
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117 WD_Cmd equ $08
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118 WD_Stat equ WD_Cmd
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119 WD_Trak equ $09
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120 WD_Sect equ $0A
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121 WD_Data equ $0B
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122
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123 * WD-17X3 Commands
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124 S$Read equ $80 Read sector
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125 S$Format equ $A0 Format track
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126 S$FrcInt equ $D0 Force interrupt
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127
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128 * Control Register Definitions
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129 C_HALT equ %10000000 Halt line to CPU is active when set
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130 C_SIDSEL equ %01000000 Side select (0 = front side, 1 = back side)
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131 C_DBLDNS equ %00100000 Density (0 = single, 1 = double)
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132 C_WPRCMP equ %00010000 Write precompensation (0 = off, 1 = on)
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133 C_MOTOR equ %00001000 Drive motor (0 = off, 1 = on)
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134 C_DRV2 equ %00000100 Drive 2 selected when set
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135 C_DRV1 equ %00000010 Drive 1 selected when set
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136 C_DRV0 equ %00000001 Drive 0 selected when set
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137
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138 mod eom,name,tylg,atrv,start,size
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139
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140 u0000 rmb DRVBEG+(DRVMEM*N.Drives)
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141 lastdrv rmb 2 Last drive table accessed (ptr)
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142 ctlimg rmb 1 Bit mask for control reg (drive #, side,etc)
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143 u00AA rmb 1 drive change flag
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144 sectbuf rmb 2 Ptr to 512 byte sector buffer
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145 currside rmb 1 head flag; 0=front 1 = back
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146 u00AE rmb 1 LSB of LSN
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147 IFGT Level-1
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148 FBlock rmb 2 block number for format
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149 FTask rmb 1 task number for format
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150 ENDC
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151 VIRQPak rmb 2 Vi.Cnt word for VIRQ
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152 u00B3 rmb 2 Vi.Rst word for VIRQ
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153 u00B5 rmb 1 Vi.Stat byte for VIRQ (drive motor timeout)
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154 loglsn rmb 2 OS9's logical sector #
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155 * Removed next line and added two new ones. RG
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156 * PCDOS does not ask driver for any info.
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157 * physlsn rmb 2 PCDOS (512 byte sector) #
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158 flag512 rmb 1 PCDOS (512 byte sector) 0=no, 1=yes
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159 flagform rmb 1 SCII format flag
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160 size equ .
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161
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162 fcb DIR.+SHARE.+PEXEC.+PWRIT.+PREAD.+EXEC.+UPDAT.
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163
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164 name fcs /rb1773/
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165 fcb edition
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166
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167 VIRQCnt fdb TkPerSec*4 Initial count for VIRQ (4 seconds)
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168
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169 IRQPkt fcb $00 Normal bits (flip byte)
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170 fcb $01 Bit 1 is interrupt request flag (Mask byte)
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171 fcb 10 Priority byte
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172
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173 * Init
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174 *
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175 * Entry:
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176 * Y = address of device descriptor
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177 * U = address of device memory area
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178 *
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179 * Exit:
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180 * CC = carry set on error
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181 * B = error code
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182 *
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183 * New code added 09/03/2003 by Boisy G. Pitre
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184 * Write a pattern to $FF4B and read it back to verify that the hardware
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185 * does exist.
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186 Init equ *
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187 * Two new lines for SCII. RG
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188 IFNE SCII
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189 clr RW.Ctrl clear SCII control register
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190 clr flagform,u clear SCII format flag
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191 ENDC
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192 ldx V.PORT,u get Base port address
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193 lda WD_Data,x get byte at FDC Data register
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194 coma complement it to modify it
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195 sta WD_Data,x write it
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196 clrb
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197 Init2 decb delay a bit...
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198 bmi Init2
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199 suba WD_Data,x read it back
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200 lbne NoHW if not zero, we didn't read what we wrote
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201 **
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202 IFEQ Level-1
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203 clr >D.DskTmr flag drive motor as not running
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204 ELSE
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205 clr <D.MotOn flag drive motor as not running
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206 ENDC
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207 leax WD_Stat,x point to Status/Command register
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208 lda #S$FrcInt "Force Interrupt" command
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209 sta ,x send to FDC
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210 lbsr FDCDelay time delay for ~ 108 cycles
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211 lda ,x eat status register
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212 ldd #$FF*256+N.Drives 'invalid' value & # of drives
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213 leax DRVBEG,u point to start of drive tables
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214 l1 sta ,x DD.TOT MSB to bogus value
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215 sta <V.TRAK,x init current track # to bogus value
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216 leax <DRVMEM,x point to next drive table
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217 decb done all drives yet?
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218 bne l1 no, init them all
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219 leax >NMISvc,pc point to NMI service routine
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220 IFGT Level-1
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221 stx <D.NMI install as system NMI
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222 ELSE
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223 stx >D.XNMI+1 NMI jump vector operand
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224 lda #$7E JMP code
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225 sta >D.XNMI NMI jump vector opcode
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226 ENDC
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227 pshs y save device dsc. ptr
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228 leay >u00B5,u point to Vi.Stat in VIRQ packet
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229 tfr y,d make it the status register ptr for IRQ
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230 leay >IRQSvc,pc point to IRQ service routine
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231 leax >IRQPkt,pc point to IRQ packet
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232 os9 F$IRQ install IRQ
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233 puls y Get back device dsc. ptr
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234 bcs Return If we can't install IRQ, exit
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235 ldd #512 Request 512 byte sector buffer
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236 pshs u Preserve device mem ptr
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237 os9 F$SRqMem Request sector buffer
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238 tfr u,x Move ptr to sector buffer to x
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239 puls u Restore device mem ptr
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240 bcs Return If error, exit with it
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241 stx >sectbuf,u Save ptr to sector buffer
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242
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243 * GetStat
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244 *
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245 * Entry:
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246 * A = function code
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247 * Y = address of path descriptor
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248 * U = address of device memory area
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249 *
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250 * Exit:
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251 * CC = carry set on error
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252 * B = error code
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253 *
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254 GetStat clrb no GetStt calls - return, no error, ignore
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255 Return rts
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256
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257 * Term
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258 *
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259 * Entry:
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260 * U = address of device memory area
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261 *
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262 * Exit:
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263 * CC = carry set on error
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264 * B = error code
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265 *
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266 Term leay >VIRQPak,u Point to VIRQ packet
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267 IFNE H6309
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268 tfr 0,x "remove"
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269 ELSE
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270 ldx #$0000
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271 ENDC
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272 os9 F$VIRQ Remove VIRQ
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273 IFNE H6309
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274 tfr 0,x "remove"
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275 ELSE
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276 ldx #$0000
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277 ENDC
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278 leay >IRQSvc,pc point to IRQ service routine
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279 os9 F$IRQ Remove IRQ
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280 pshs u Save device mem ptr
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281 ldu >sectbuf,u Get pointer to sector buffer
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282 ldd #512 Return sector buffer memory
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283 os9 F$SRtMem
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284 puls u Restore device mem ptr
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285 clr >DPort+CtrlReg shut off drive motors
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286 IFEQ Level-1
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287 clr >D.DskTmr Clear out drive motor timeout flag
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288 ELSE
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289 clr <D.MotOn Clear out drive motor timeout flag
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290 ENDC
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291 ex rts return
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292
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293 * Check if 512 byte sector conversion needed
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294 * Entry: B:X=LSN
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295 * U=Static mem ptr
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296 * Y=Path dsc. ptr
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297 * Exit: X=New LSN (same as original for 256 byte sectors, 1/2 of original
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298 * for 512 byte sectors
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299 * regD changed
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300 Chk512 equ *
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301 clr flag512,u set to 256 byte sector
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302 stx >loglsn,u save OS9 LSN
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303 lda <PD.TYP,y get device type from path dsc.
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304 anda #%00000100 mask out all but 512 byte sector flag
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305 bne Log2Phys 512 byte sectors, go process
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306 rts RG
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307
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308 * 512 byte sector processing goes here
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309 * regB should be saved and not just cleared at end because there is
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310 * a subsequent tst for the msb of lsn. The test is pointless if B
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311 * is changed.
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312 Log2Phys pshs b save MSB of LSN; new RG
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313 * Minor inefficiencies here that I have changed, RG
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314 tfr x,d
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315 IFNE H6309
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316 lsrd
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317 ELSE
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318 lsra
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319 rorb
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320 ENDC
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321 tfr d,x move new LSN back to regX
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322 * New line for stock SCII controller with 256 max no-halt.
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323 inc flag512,u set to 512 byte sector
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324 puls b,pc regB will be tested later for >0
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325
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326 start lbra Init
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327 bra Read
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328 nop
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329 lbra Write
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330 bra GetStat
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331 nop
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332 lbra SetStat
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333 bra Term
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334 nop
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335
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336 * Read
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337 *
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338 * Entry:
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339 * B = MSB of LSN
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340 * X = LSB of LSN
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341 * Y = address of path descriptor
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342 * U = address of device memory area
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343 *
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344 * Exit:
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345 * CC = carry set on error
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346 * B = error code
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347 *
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348 Read bsr Chk512 go check for 512 byte sector/adjust if needed
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349 lda #%10010001 error flags (see Disto SCII source)
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350 pshs x preserve sector #
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351 lbsr ReadWithRetry go read the sector
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352 puls x restore sector #
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353 bcs ex if error, exit
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354 pshs y,x save path dsc ptr & LSN
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355 leax ,x LSN0?, ie. tstx
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356 bne L012D no, go calculate normally
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357 puls y,x yes, restore path dsc ptr & LSN
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358 lda <PD.TYP,y get type from path dsc.
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359 bita #TYP.NSF standard OS-9 format?
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360 beq L00F0 yes, skip ahead
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361 lbsr MakeDTEntry else make a drive table entry
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362 pshs y,x save path dsc ptr
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363 bra L012D
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364
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365 * LSN0, standard OS-9 format - copy part of LSN0 into drive table
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diff changeset
366 L00F0 ldx >sectbuf,u Get ptr to sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
367 pshs y,x Preserve path dsc. ptr & sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
368 ldy >lastdrv,u Get last drive table accessed ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
369 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
370 ldw #DD.SIZ # bytes to copy from new LSN0 to drive table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
371 tfm x+,y+ Copy them
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
372 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
373 ldb #DD.SIZ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
374 L00F0Lp lda ,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
375 sta ,y+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
376 decb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
377 bne L00F0Lp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
378 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
379 ldy >lastdrv,u Get drive table ptr back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
380 lda <DD.FMT,y Get format for disk in drive
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
381 ldy 2,s restore path descriptor pointer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
382 ldb <PD.DNS,y Get path's density settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
383 bita #FMT.DNS Disk in drive double density?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
384 beq L0115 No, all drives can read single, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
385 bitb #DNS.MFM Can our path dsc. handle double density?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
386 beq erbtyp No, illegal
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
387 L0115 bita #FMT.TDNS Is new disk 96/135 tpi?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
388 beq L011D No, all drives handle 48 tpi, so skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
389 bitb #DNS.DTD Can path dsc. handle 96/135 tpi?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
390 beq erbtyp No, illegal
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
391 L011D bita #FMT.SIDE Is new disk double sided?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
392 beq L0128 No, all drives handle single sided, we're done
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
393 lda <PD.SID,y Get # sides path dsc. can handle
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
394 suba #2 sides higher or equal to 2?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
395 blo erbtyp Yes, exit with illegal type error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
396 L0128 clrb No error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
397 * LSN's other than 0 come straight here
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
398 L012D ldy 2,s Get path dsc. ptr back??
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
399 ldx PD.BUF,y Get path dsc. buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
400 * lda <PD.TYP,y Get path dsc. disk type, RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
401 ldy >sectbuf,u Get ptr to sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
402 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
403 ldw #256 OS9 sector size (even if physical was 512)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
404 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
405 * anda #%00000100 Mask out all but 512 byte sector flag, RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
406 * Next replaces the two lines removed, RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
407 tst flag512,u Is it a 512 byte sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
408 beq L014B If normal sector, just copy it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
409 ldd >loglsn,u Get OS9's LSN (twice of the 'real' 512 sector)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
410 andb #$01 Mask out all but odd/even sector indicator
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
411 beq L014B Even, use 1st half of 512 byte sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
412 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
413 addr w,y Odd, bump sector buffer ptr to 2nd half
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
414 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
415 leay 256,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
416 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
417 L014B equ *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
418 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
419 tfm y+,x+ Copy from physical sector buffer to PD buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
420 puls pc,y,x restore path dsc & sector buffer ptrs & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
421 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
422 pshs d
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
423 clrb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
424 L014BLp lda ,y+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
425 sta ,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
426 decb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
427 bne L014BLp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
428 puls pc,y,x,d restore path dsc & sector buffer ptrs & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
429 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
430
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
431 erbtyp comb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
432 ldb #E$BTyp Error - wrong type error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
433 puls pc,y,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
434
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
435 **********************
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
436 * Read error - retry handler
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
437 Retry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
438 bcc ReadWithRetry Normal retry, try reading again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
439 pshs x,d Preserve regs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
440 lbsr sktrk0 Seek to track 0 (attempt to recalibrate)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
441 puls x,d Restore regs & try reading again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
442
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
443
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
444 * Read With Retry: Do read with retries
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
445 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
446 * ENTER reg B,X=working lsn on disk
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
447 * Y=path descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
448 * U=driver data
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
449 * A=retry sequence mix of read & seek track 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
450 * EXIT X,Y,U preserved; D,CC changed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
451 * B=error if any
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
452 * CC=error flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
453 ReadWithRetry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
454 pshs x,d Preserve regs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
455 bsr ReadSector Go read sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
456 puls x,d Restore regs (A=retry flags)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
457 lbcc L01D7 No error, return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
458 lsra Shift retry flags
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
459 bne Retry Still more retries allowed, go do them
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
460 * otherwise, final try before we give up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
461 ReadSector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
462 lbsr L02AC Do double-step/precomp etc. if needed, seek
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
463 lbcs L01D7 Error somewhere, exit with it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
464 L0176 ldx >sectbuf,u Get physical sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
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diff changeset
465 ldb #S$Read Read sector command
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
466 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
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diff changeset
467 * If SCII not hacked for 512 byte no-halt, must use halt for 512b sectors RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
468 IFEQ SCIIHACK
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
469 clra SCII normal mode, normal NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
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diff changeset
470 tst flag512,u SCII must use halt mode for 512 byte sectors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
471 bne L0176B
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
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diff changeset
472 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
473 lda #7 SCII read, buffered mode, masked NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
474 bsr L01A1B send commands and wait
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
475 * New lines needed because the SCII has error other than OS-9 errors. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
476 bcs ngood
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
477 * This now becomes a subroutine call. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
478 * lbcs L03AF get the errors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
479 lbsr L03AF get the errors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
480 bcc good
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
481 ngood rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
482 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
483 good pshs y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
484 ldw #128 set counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
485 ldy #RW.DAT source of data
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
486 IFNE SCIIHACK
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
487 tst flag512,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
488 beq sc2rlp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
489 ldw #256 bump up counter to 512 byte sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
490 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
491 * Don't use tfm if no halt important else need orcc #$50 for tfm
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
492 * If an interrupt occurs during a tfm transfer, the SCII counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
493 * will update but the tfm will repeat a byte and lose track.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
494 * If orcc #$50 used, then key presses may be lost even with no-halt
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
495 * mode.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
496 sc2rlp ldd ,y read two bytes from SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
497 std ,x++ transfer two bytes to system buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
498 decw update counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
499 bne sc2rlp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
500 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
501 good ldy #128
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
502 IFNE SCIIHACK
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
503 tst flag512,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
504 beq sc2rlp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
505 ldy #256
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
506 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
507 sc2rlp ldd >RW.DAT
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
508 std ,x++
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
509 leay -1,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
510 bne sc2rlp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
511 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
512 clrb no errors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
513 puls y,pc
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
514 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
515
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
516 L0176B bsr L01A1 Send to controller & time delay to let it settle
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
517 *** Next few lines are commented out for blobstop patches
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
518 *L0180 bita >DPort+WD_Stat check status register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
519 * bne L0197 eat it & start reading sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
520 * leay -1,y bump timeout timer down
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
521 * bne L0180 keep trying until it reaches 0 or sector read
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
522 * lda >ctlimg,u get current drive settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
523 * ora #C_MOTOR turn drive motor on
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
524 * sta >DPort+CtrlReg send to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
525 * puls y,cc restore regs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
526 * lbra L03E0 exit with Read Error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
527 *** Blobstop fixes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
528 stb >DPort+CtrlReg send B to control register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
529 nop allow HALT to take effect
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
530 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
531 bra L0197 and a bit more time
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
532 * Read loop - exited with NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
533 * Entry: X=ptr to sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
534 * B=Control register settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
535 L0197 lda >DPort+WD_Data get byte from controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
536 sta ,x+ store into sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
537 * stb >DPort+CtrlReg drive info
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
538 nop -- blobstop fix
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
539 bra L0197 Keep reading until sector done
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
540
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
541 L01A1 orcc #IntMasks Shut off IRQ & FIRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
542 * No-halt mode must enter here, skipping IRQ shutoff.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
543 L01A1B stb >DPort+WD_Cmd Send command
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
544 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
545 sta >RW.Ctrl tell SCII what to do
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
546 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
547 L01A1C ldb #C_DBLDNS+C_MOTOR Double density & motor on
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
548 orb >ctlimg,u Merge with current drive settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
549 stb >DPort+CtrlReg Send to control register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
550 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
551 tst flagform,u Format uses halt mode
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
552 bne s512
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
553 IFEQ SCIIHACK
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
554 tst flag512,u SCII uses halt with 512 byte sectors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
555 beq s256
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
556 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
557 bra s256
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
558 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
559 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
560 s512 ldb #C_HALT+C_DBLDNS+C_MOTOR Enable halt, double density & motor on
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
561 orb >ctlimg,u Merge that with current drive settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
562 lbra FDCDelay Time delay to wait for command to settle
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
563 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
564 s256 ldb #4 normal mode, NMI masked
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
565 lda #255 time out slices
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
566 pshs a,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
567 SC2tmr1 ldx #1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
568 lbsr Delay sleep or timer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
569 dec ,s count
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
570 beq tmout
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
571 tst >RW.Ctrl check status
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
572 bmi SC2tmr1 loop on not ready
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
573 stb RW.Ctrl clear SCII but don't generate NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
574 clrb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
575 puls a,x,pc
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
576 tmout stb RW.Ctrl clear SCII buffer counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
577 lda #$D0 force interrupt
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
578 sta DPort+WD_Cmd
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
579 comb set carry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
580 puls a,x,pc
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
581 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
582
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
583 * Delay for some number of ticks (1 tick = 1/60 second).
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
584 * For a hard delay, we need to delay for 14833 cycles at .89MHz or
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
585 * 29666 cycles at 1.78MHz
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
586 * Entry: X = number of ticks to delay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
587 Delay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
588 pshs d [5+] [4+]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
589 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
590 ldd <D.Proc [6] [5] process pointer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
591 cmpd <D.SysPrc [is it the system?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
592 beq hardloop [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
593 os9 F$Sleep if not system then sleep
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
594 puls d,pc [5+] [4+]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
595 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
596 hardloop tfr x,d we want X in A,B
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
597 l1@ equ *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
598 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
599 ldx #1482/2 [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
600 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
601 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
602 ldx #1854 [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
603 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
604 ldx #1482 [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
605 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
606 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
607 l2@ nop [2] [1]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
608 nop [2] [1]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
609 nop [2] [1]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
610 leax -1,x [4+] [4+]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
611 bne l2@ [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
612 subd #$0001 [4] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
613 bne l1@ [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
614 puls d,pc [5+] [4+]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
615
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
616 * Write
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
617 * Entry:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
618 * B = MSB of LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
619 * X = LSB of LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
620 * Y = address of path descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
621 * U = address of device memory area
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
622 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
623 * Exit:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
624 * CC = carry set on error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
625 * B = error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
626 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
627 Write lbsr Chk512 go adjust LSN for 512 byte sector if needed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
628 * Next line was lda #%1001001 which was an error RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
629 lda #%10010001 retry flags for I/O errors (see Disto SCII source)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
630 L01C4 pshs x,d preserve LSN, retries
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
631 bsr L01E8 go write the sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
632 puls x,d restore LSN, retries
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
633 bcs L01D8 error writing, go to write retry handler
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
634 tst <PD.VFY,y no error, do we want physical verify?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
635 bne L01D6 no, exit without error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
636 lbsr verify go re-read & verify 64 out of 256 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
637 bcs L01D8 error on verify, go to write retry handler
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
638 L01D6 clrb no error & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
639 L01D7 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
640
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
641 * Write error retry handler
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
642 L01D8 lsra Shift retry flags
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
643 lbeq L03AF Too many retries, exit with error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
644 bcc L01C4 Normal retry, attemp to re-write sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
645 pshs x,d Preserve flags & sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
646 lbsr sktrk0 Seek to track 0 (attempt to recalibrate)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
647 puls x,d Restore flags & sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
648 bra L01C4 Try re-writing now
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
649
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
650 * 512 byte sector write here
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
651 L01E8 lbsr L02AC Go do double-step/write precomp if needed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
652 bcs L01D7 Error, exit with it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
653 pshs y,d Preserve path dsc. ptr & LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
654 * Since I have modified chk512 the next two lines are replaced. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
655 * lda <PD.TYP,y Get device type
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
656 * anda #%00000100 512 byte sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
657 tst flag512,u go if 256 byte sectors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
658 beq L020D Not 512 then skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
659 lbsr L0176 Go read the sector in
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
660 ldd >loglsn,u Get OS9 LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
661 andb #$01 Even or odd?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
662 beq L020D Even, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
663 ldx >sectbuf,u Get physical sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
664 leax >$0100,x Point to 2nd half
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
665 bra L0211 Copy caller's buffer to 2nd half of sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
666
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
667 L020D ldx >sectbuf,u Get physical sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
668
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
669 L0211 ldy PD.BUF,y Get path dsc. buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
670 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
671 ldw #256 Copy write buffer to sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
672 tfm y+,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
673 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
674 clrb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
675 L0211Lp lda ,y+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
676 sta ,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
677 decb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
678 bne L0211Lp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
679 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
680 puls y,d Get path dsc. ptr & LSN back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
681 ldx >sectbuf,u Get physical sector buffer ptr again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
682 * See read routine for explanation of SCII code. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
683 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
684 IFEQ SCIIHACK
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
685 clra SCII write, normal mode & NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
686 tst flag512,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
687 bne wr512
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
688 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
689 lda #4 SCII normal mode, masked NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
690 sta RW.Ctrl tell SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
691 pshs y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
692 ldy #RW.Dat Send data to SCII RAM buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
693 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
694 ldw #128
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
695 tst flag512,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
696 beq wrbuf
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
697 ldw #256
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
698 wrbuf ldd ,x++
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
699 std ,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
700 decw
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
701 bne wrbuf
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
702 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
703 ldy #128
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
704 tst flag512,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
705 beq wrbuf
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
706 ldy #256
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
707 wrbuf ldd ,x++
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
708 std >RW.DAT
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
709 leay -1,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
710 bne wrbuf
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
711 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
712 puls y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
713 ldb #$A0 Write sector command
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
714 lda #6 SCII masked NMI, buffered mode, write
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
715 * See Read section for explanation of error changes below. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
716 * lbra L01A1B send command to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
717 lbsr L01A1B send command to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
718 bcs wngood SCII error, then go
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
719 lbra L03AF check for OS-9 errors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
720 wngood rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
721 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
722 wr512 ldb #S$Format
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
723
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
724 * Format track comes here with B=$F0 (write track)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
725 * as does write sector with B=$A0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
726 *WrTrk pshs y,cc Preserve path dsc. ptr & CC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
727 WrTrk lbsr L01A1 Send command to controller (including delay)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
728 *** Commented out for blobstop fixes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
729 *L0229 bita >DPort+WD_Stat Controller done yet?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
730 * bne L0240 Yes, go write sector out
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
731 * leay -$01,y No, bump wait counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
732 * bne L0229 Still more tries, continue
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
733 * lda >ctlimg,u Get current drive control register settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
734 * ora #C_MOTOR Drive motor on (but drive select off)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
735 * sta >DPort+CtrlReg Send to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
736 * puls y,cc Restore regs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
737 * lbra L03AF Check for errors from status register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
738
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
739 *** added blobstop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
740 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
741 lda FBlock+1,u get the block number for format
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
742 beq L0230 if not format, don't do anything
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
743 sta >$FFA1 otherwise map the block in
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
744 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
745 L0230 stb >DPort+CtrlReg send data to control register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
746 * These lines added to match read routine. Should be better timing. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
747 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
748 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
749 bra L0240 wait a bit for HALT to enable
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
750
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
751 * Write sector routine (Entry: B= drive/side select) (NMI will break out)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
752 * Part of timing change mentioned above. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
753 *L0240 nop --- wait a bit more
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
754 L0240 lda ,x+ Get byte from write buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
755 sta >DPort+WD_Data Save to FDC's data register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
756 * EAT 2 CYCLES: TC9 ONLY (TRY 1 CYCLE AND SEE HOW IT WORKS)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
757 IFEQ TC9-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
758 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
759 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
760 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
761 * See above. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
762 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
763 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
764 * stb >DPort+CtrlReg Set up to read next byte
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
765 bra L0240 Go read it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
766
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
767 * NMI routine
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
768 NMISvc leas R$Size,s Eat register stack
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
769 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
770 ldx <D.SysDAT get pointer to system DAT image
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
771 lda 3,x get block number 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
772 sta >$FFA1 map it back into memory
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
773 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
774 andcc #^IntMasks turn IRQ's on again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
775 ldb >DPort+WD_Stat Get status register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
776 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
777 clr RW.Ctrl Clear SCII command register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
778 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
779 bitb #%00000100 Did we lose data in the transfer?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
780 lbeq L03B2 Otherwise, check for drive errors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
781 comb -- blobstop error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
782 ldb #E$DevBsy -- device busy
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
783 rts -- and exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
784
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
785 verify pshs x,d
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
786 * Removed unneeded code. Data never sent to PD.BUF anyway so there is
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
787 * no need to redirect the PD.BUF pointer. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
788 * ldx PD.BUF,y Get write buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
789 * pshs x Preserve it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
790 * ldx >sectbuf,u Get sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
791 * stx PD.BUF,y Save as write buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
792 * ldx 4,s
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
793 lbsr ReadSector Go read sector we just wrote
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
794 * puls x Get original write buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
795 * stx PD.BUF,y Restore path dsc. version
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
796 bcs L02A3 If error reading, exit with it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
797 ldx PD.BUF,y Get system buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
798 pshs u,y Preserve device mem, path dsc. ptrs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
799 * See change in chk512 routine. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
800 * ldb <PD.TYP,y Get type from path dsc.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
801 ldy >sectbuf,u Get sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
802 * andb #%00000100 512 byte sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
803 tst flag512,u 512 byte sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
804 beq L028D No, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
805 ldd >loglsn,u Get OS9's sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
806 andb #$01 Odd/even sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
807 beq L028D Even; compare first half
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
808 leay >$0100,y Odd, compare second half
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
809 L028D tfr x,u Move PD.BUF ptr to U (since cmpx is faster)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
810 clra check all 256 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
811 L028F ldx ,u++ Get 2 bytes from original write buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
812 cmpx ,y++ Same as corresponding bytes in re-read sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
813 bne vfybad No, error & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
814 inca
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
815 bpl L028F No, continue
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
816 bra L02A1 carry is clear by virtue of last cmpx
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
817 vfybad comb set carry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
818 L02A1 puls u,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
819 L02A3 puls pc,x,d
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
820
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
821 L02A5 pshs a Save Caller's track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
822 ldb <V.TRAK,x Get track # drive is currently on
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
823 bra L02E9 Go save it to controller & continue
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
824
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
825 L02AC lbsr L0376 Go set up controller for drive, spin motor up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
826 bsr L032B Get track/sector # (A=Trk, B=Sector)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
827 pshs a Save track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
828 lda >currside,u Get side 1/2 flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
829 beq L02C4 Side 1, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
830 lda >ctlimg,u Get control register settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
831 ora #C_SIDSEL Set side 2 (drive 3) select
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
832 sta >ctlimg,u Save it back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
833 L02C4 lda <PD.TYP,y Get drive type settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
834 bita #%00000010 ??? (Base 0/1 for sector #?)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
835 bne L02CC Skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
836 incb Bump sector # up by 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
837 L02CC stb >DPort+WD_Sect Save into Sector register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
838 ldx >lastdrv,u Get last drive table accessed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
839 ldb <V.TRAK,x Get current track # on device
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
840 lda <DD.FMT,x Get drive format specs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
841 lsra Shift track & bit densities to match PD
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
842 eora <PD.DNS,y Check for differences with path densities
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
843 anda #%00000010 Keep only 48 vs. 96/135 tpi differences
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
844 pshs a Save differences
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
845 lda 1,s Get track # back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
846 tst ,s+ Are tpi's different?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
847 beq L02E9 No, continue normally
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
848 lsla Yes, multiply track # by 2 ('double-step')
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
849 lslb Multiply current track # by 2 ('double-step')
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
850 L02E9 stb >DPort+WD_Trak Save current track # onto controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
851
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
852 * From here to the line before L0307 is for write precomp, but is not used.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
853 * Unless write precomp is needed, all of this is useless
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
854 * I think most (if not all) drives do NOT need precomp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
855 IFEQ PRECOMP-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
856 ldb #21 Pre-comp track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
857 pshs b Save it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
858 ldb <PD.DNS,y Get current density settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
859 andb #%00000010 Just want to check track density
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
860 beq L02F9 48 tpi, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
861 lsl ,s Multiply pre-comp value by 2 ('double-step')
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
862 L02F9 cmpa ,s+ Is track # high enough to warrant precomp?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
863 bls L0307 No, continue normally
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
864 ldb >ctlimg,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
865 orb #C.WRPCMP Turn on Write precomp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
866 stb >ctlimg,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
867 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
868
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
869 L0307 tst >u00AA,u ??? Get flag (same drive flag?)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
870 bne L0314 no, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
871 ldb ,s get track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
872 cmpb <V.TRAK,x same as current track on this drive?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
873 beq L0321 yes, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
874 L0314 sta >DPort+WD_Data save track # to data register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
875 ldb <PD.STP,y get stepping rate
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
876 andb #%00000011 just keep usable settings (6-30 ms)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
877 eorb #%00011011 set proper bits for controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
878 lbsr L03E4 send command to controller & time delay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
879 L0321 puls a get track # back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
880 sta <V.TRAK,x save as current track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
881 sta >DPort+WD_Trak save to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
882 clrb no error & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
883 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
884
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
885 * Entry: B:X LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
886 * Exit: A=Track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
887 * B=Sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
888 * <currside=00 = Head 1 , $FF = Head 2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
889 L032B tstb Sector # > 65535?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
890 bne L033F Yes, illegal for floppy
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
891 tfr x,d Move sector # to D
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
892 leax ,x LSN 0? ie. "tstx"
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
893 beq L0371 Yes, exit this routine
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
894 ldx >lastdrv,u Get previous drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
895 cmpd DD.TOT+1,x Within range of drive spec?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
896 blo L0343 Yes, go calculate track/sector #'s
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
897 L033F comb Exit with Bad sector # error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
898 ldb #E$Sect
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
899 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
900
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
901 * Calculate track/sector #'s?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
902 * These two sections could be combined into one with a final
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
903 * test of DD.FMT. Then currside can be set and regA can be lsra
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
904 * as needed. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
905 L0343 stb >u00AE,u Save LSB of LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
906 clr ,-s Clear track # on stack
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
907 ldb <DD.FMT,x Get drive format
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
908 lsrb Shift out # sides into carry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
909 ldb >u00AE,u Get LSB of LSN again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
910 bcc L0367 Single sided drive, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
911 bra L035D Double sided drive, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
912 * Double sided drive handling here
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
913 L0355 com >currside,u Odd/even sector track flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
914 bne L035D Odd, so don't bump track # up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
915 inc ,s Bump up track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
916
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
917 * Changed this to more effient code. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
918 *L035D subb DD.TKS,x Subtract # sectors/track
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
919 * sbca #$00
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
920 L035D subd DD.SPT,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
921 bcc L0355 Still more sectors left, continue
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
922 bra L036D Wrapped, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
923 * Single sided drive handling here
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
924 L0365 inc ,s Bump track # up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
925
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
926 * See above. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
927 *L0367 subb DD.TKS,x Subtract # sectors/track
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
928 * sbca #$00
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
929 L0367 subd DD.SPT,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
930 bcc L0365 Still more, go bump the track up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
931 * Next possible because upper limit is 256 sectors/track. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
932 L036D addb DD.TKS,x Bump sector # back up from negative value
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
933 puls a Get the track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
934 L0371 rts A=track #, B=Sector #, <currside=Odd
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
935
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
936 * Drive control register bit mask table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
937 * May want an option here for double sided SDDD disks ex. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
938 * fcb $1 drive0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
939 * fcb $2 drive1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
940 * fcb $41 drive2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
941 * fcb $42 drive3
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
942 * fcb $4 drive4
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
943 * fcb $44 drive5
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
944
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
945 L0372 fcb $01 Drive 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
946 fcb $02 Drive 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
947 fcb $04 Drive 2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
948 fcb $40 Drive 3 / Side select
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
949
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
950 * Changes regD; X,Y,U preserved
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
951 L0376 clr >u00AA,u clear drive change flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
952 chkdrv lda <PD.DRV,y Get drive # requested
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
953 * It is possible to have more than 4 drive # so the change below. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
954 * cmpa #4 Drive 0-3?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
955 cmpa #N.Drives Drive 0-6 if alternate table used?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
956 blo L0385 Yes, continue normally
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
957 NoHW comb Illegal drive # error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
958 ldb #E$Unit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
959 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
960
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
961 * Entry: A=drive #, X=LSN (Physical, not OS9 logical if PCDOS disk)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
962 L0385 pshs x,d Save sector #, drive # & B???
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
963 leax >L0372,pc Point to drive bit mask table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
964 ldb a,x Get bit mask for drive # we want
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
965 stb >ctlimg,u Save mask
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
966 leax DRVBEG,u Point to beginning of drive tables
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
967 ldb #DRVMEM Get size of each drive table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
968 mul Calculate offset to drive table we want
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
969 leax d,x Point to it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
970 cmpx >lastdrv,u Same as Last drive table accessed?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
971 beq L03A6 Yes, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
972 stx >lastdrv,u Save new drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
973 com >u00AA,u Set drive change flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
974 L03A6 clr >currside,u Set side (head) flag to side 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
975 lbsr L04B3 Go set up VIRQ to wait for drive motor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
976 puls pc,x,d Restore sector #,drive #,B & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
977
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
978 L03AF ldb >DPort+WD_Stat Get status register from FDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
979 * This line needed when returning to Disk Basic but probably
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
980 * not needed for OS-9. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
981 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
982 clr RW.Ctrl return SCII to halt mode
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
983 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
984 L03B2 bitb #%11111000 any of the error bits set?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
985 beq L03CA No, exit without error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
986 aslb Drive not ready?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
987 bcs L03CC Yes, use that error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
988 aslb Write protect error?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
989 bcs L03D0 Yes, use that error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
990 aslb Write fault error?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
991 bcs L03D4 Yes, use that error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
992 aslb Sector not found?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
993 bcs L03D8 Yes, use Seek error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
994 aslb CRC error?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
995 bcs L03DC Yes, use that error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
996 L03CA clrb No error & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
997 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
998
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
999 L03CC ldb #E$NotRdy not ready
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1000 fcb $8C skip 2 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1001
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1002 L03D0 ldb #E$WP write protect
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1003 fcb $8C skip 2 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1004
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1005 L03D4 ldb #E$Write write error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1006 fcb $8C
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1007
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1008 L03D8 ldb #E$Seek seek error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1009 fcb $8C
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1010
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1011 L03DC ldb #E$CRC CRC error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1012 * fcb $8C
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1013
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1014 *L03E0 ldb #E$Read Read error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1015 orcc #Carry set carry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1016 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1017
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1018 L03E4 bsr L0404 Send command to controller & waste some time
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1019 L03E6 ldb >DPort+WD_Stat Check FDC status register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1020 bitb #$01 Is controller still busy?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1021 beq L0403 No, exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1022 ldd >VIRQCnt,pc Get initial count value for drive motor speed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1023 std >VIRQPak,u Save it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1024 * Again, I'm trying to match Kevin Darling code. It may not be needed. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1025 pshs x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1026 ldx #1 Sleep remainder of slice
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1027 lbsr Delay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1028 puls x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1029 bra L03E6 Wait for controller to finish previous command
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1030
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1031 * Send command to FDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1032 L03F7 lda #C_MOTOR
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1033 * lda #%00001000 Mask in Drive motor on bit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1034 ora >ctlimg,u Merge in drive/side selects
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1035 sta >DPort+CtrlReg Turn the drive motor on & select drive
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1036 stb >DPort+WD_Cmd Save command & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1037 L0403 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1038
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1039 L0404 bsr L03F7 Go send command to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1040
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1041 * This loop has been changed from nested LBSRs to timing loop.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1042 * People with crystal upgrades should modify the loop counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1043 * to get a 58+ us delay time. MINIMUM 58us.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1044 FDCDelay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1045 pshs a 14 cycles, plus 3*loop counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1046 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1047 lda #18 (only do about a 100 cycle delay for now)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1048 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1049 lda #29 (only do about a 100 cycle delay for now)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1050 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1051 L0409 deca for total ~63 us delay (123 cycles max.)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1052 bne L0409
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1053 puls a,pc restore register and exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1054
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1055 * SetStat
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1056 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1057 * Entry:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1058 * A = function code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
1059 * Y = address of path descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1060 * U = address of device memory area
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1061 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1062 * Exit:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1063 * CC = carry set on error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1064 * B = error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1065 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1066 SetStat ldx PD.RGS,y Get caller's register stack ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1067 ldb R$B,x Get function code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1068 cmpb #SS.WTrk Write track?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1069 beq SSWTrk Yes, go do it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1070 cmpb #SS.Reset Restore head to track 0?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
1071 lbeq sktrk0 Yes, go do it --- beq
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1072 comb set carry for error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1073 ldb #E$UnkSvc return illegal service request error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1074 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1075
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1076 SSWTrk pshs u,y preserve register stack & descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1077
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
1078 * Level 2 Code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1079 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
1080
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
1081 *--- new code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
1082 ldb #1 1 block to allocate
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1083 os9 F$AllRAM allocate some RAM
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
1084 lbcs L0489 error out if at all
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1085 leax >FBlock,u point to 'my' DAT image
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1086 std ,x save a copy of the block
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1087 os9 F$ResTsk reserve a task number for the copy
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1088 bcs FError error out
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1089 stb 2,x save temporary task number in FTask,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1090 lslb 2 bytes per entry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1091 ldu <D.TskIPt get task image table pointer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1092 stx b,u save pointer to the task's DAT image
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1093 lsrb get the right number again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1094 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1095 tfr 0,u destination is address 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1096 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1097 ldu #$0000
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1098 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1099 *--- end new code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1100
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1101 ldx 2,s get pointer to descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1102 * stu >FBlock,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1103 ldx <D.Proc Get current process ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1104 lda P$Task,x Get task # for current process
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1105 * ldb <D.SysTsk Get system task #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1106 ldy ,s
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1107 ldx PD.RGS,y Get register stack ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1108 ldx R$X,x Get ptr to caller's track buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1109 ldy #$1A00 Size of track buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1110 os9 F$Move Copy from caller to temporary task
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1111 bcs L0479 Error copying, exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1112 puls u,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1113 pshs u,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1114
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1115 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1116 * End of Level 2 Code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1117
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1118 lbsr L0376 Go check drive #/wait for it to spin up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1119 ldx PD.RGS,y Get caller's register stack ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1120 ldb R$Y+1,x Get caller's side/density
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1121 bitb #$01 Check side
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1122 beq L0465 Side 1, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1123 * I think this next line is not needed. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1124 com >currside,u * Why? This is normally used with
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1125 * calculate track. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1126 ldb >ctlimg,u Get current control register settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1127 * orb #%01000000 Mask in side 2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1128 orb #C_SIDSEL Mask in side 2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1129 stb >ctlimg,u Save updated control register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1130 L0465 lda R$U+1,x Get caller's track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1131 ldx >lastdrv,u Get current drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1132 lbsr L02A5
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1133 bcs L0489
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1134 ldb #$F0 Write track command
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1135 *---
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1136 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1137 ldx PD.RGS,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1138 ldx R$X,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1139 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1140 ldx #$2000 start writing from block 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1141 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1142
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1143 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1144 lda #1 normal unbuffered write
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1145 * Next line prevents WrTrk from switching to SCII buffered mode. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1146 sta flagform,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1147 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1148 lbsr WrTrk Go write the track
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1149 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1150 clr flagform,u permit no-halt mode RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1151 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1152
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1153 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1154 L0479 ldu 2,s
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1155 pshs b,cc Preserve error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1156 ldb >FTask,u point to task
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1157 os9 F$RelTsk release the task
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1158 fcb $8C skip 2 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1159
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1160 * format comes here when block allocation passes, but task allocation
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1161 * gives error. So er de-allocate the block.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1162 FError
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1163 pshs b,cc save error code, cc
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1164 ldx >FBlock,u point to block
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1165 ldb #1 1 block to return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1166 os9 F$DelRAM de-allocate image RAM blocks
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1167 clr FBlock+1,u ensure that the block # in FBlock is zero.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1168 puls b,cc Restore error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1169 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1170
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1171 L0489 puls pc,u,y Restore regs & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1172
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1173 * seek the head to track 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1174 sktrk0 lbsr chkdrv
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1175 ldx >lastdrv,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1176 clr <$15,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1177 lda #1 was 5 but that causes head banging
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1178 L0497 ldb <PD.STP,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1179 andb #%00000011 Just keep usable settings (6-30 ms)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1180 eorb #%01001011 Set proper bits for controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1181 pshs a
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1182 lbsr L03E4
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1183 puls a
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1184 deca
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1185 bne L0497
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1186 ldb <PD.STP,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1187 andb #%00000011 Just keep usable settings (6-30 ms)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1188 eorb #%00001011 Set proper bits for controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1189 lbra L03E4
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1190
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1191 L04B3 pshs y,x,d Preserve regs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1192 ldd >VIRQCnt,pc Get VIRQ initial count value
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1193 std >VIRQPak,u Save it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1194 lda >ctlimg,u ?Get drive?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1195 ora #C_MOTOR Turn drive motor on for that drive
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1196 * ora #%00001000 Turn drive motor on for that drive
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1197 sta >DPort+CtrlReg Send drive motor on command to FDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1198 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1199 lda >D.DskTmr Get VIRQ flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1200 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1201 lda <D.MotOn Get VIRQ flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1202 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1203 bmi L04DE Not installed yet, try installing it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1204 bne L04E0 Drive already up to speed, exit without error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1205
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1206 * Drive motor speed timing loop (could be F$Sleep call now) (was over .5 sec)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1207 * 32 was not sufficient for one of my drives. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1208 ldx #50 wait for 32 ticks; increased it RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1209 lbsr Delay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1210
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1211 L04DE bsr InsVIRQ Install VIRQ to wait for drive motors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1212 L04E0 clrb No error & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1213 puls pc,y,x,d
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1214
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1215 InsVIRQ lda #$01 Flag drive motor is up to speed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1216 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1217 sta >D.DskTmr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1218 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1219 sta <D.MotOn
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1220 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1221 ldx #$0001 Install VIRQ entry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1222 leay >VIRQPak,u Point to packet
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1223 clr Vi.Stat,y Reset Status byte
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1224 ldd >VIRQCnt,pc Get initial VIRQ count value
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1225 os9 F$VIRQ Install VIRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1226 bcc VIRQOut No error, exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1227 lda #$80 Flag that VIRQ wasn't installed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1228 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1229 sta >D.DskTmr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1230 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1231 sta <D.MotOn
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1232 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1233 VIRQOut clra
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1234 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1235
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1236 * IRQ service routine for VIRQ (drive motor time)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1237 * Entry: U=Ptr to VIRQ memory area
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1238 IRQSvc pshs a
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1239 lda <D.DMAReq
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1240 beq L0509
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1241 bsr InsVIRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1242 bra IRQOut
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1243 L0509 sta >DPort+CtrlReg
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1244 * I changed this to a clear. Don't see the point of an AND. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1245 * IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1246 * aim #$FE,>u00B5,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1247 * ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1248 * lda u00B5,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1249 * anda #$FE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1250 * sta u00B5,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1251 * ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1252 * fdb u00B5 --- so changes in data size won't affect anything
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1253 clr u00B5,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1254 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1255 clr >D.DskTmr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1256 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1257 clr <D.MotOn
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1258 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1259 IRQOut puls pc,a
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1260
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1261 * Non-OS9 formatted floppies need a drive table entry constructed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1262 * by hand since there is no RBF LSN0.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1263 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1264 * Entry: X=LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1265 * Y=Path dsc. ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
boisy
parents: 1620
diff changeset
1266 * U=Device mem ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1267 MakeDTEntry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1268 pshs x Preserve Logical sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1269 ldx >lastdrv,u Get last drive table accessed ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1270 clra
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1271 pshs x,a Save ptr & NUL byte
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1272 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1273 ldw #20 Clear 20 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1274 tfm s,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1275 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1276 ldb #20
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1277 L051ALp clr ,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1278 decb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1279 bne L051ALp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1280 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1281 puls x,a Eat NUL & get back drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1282 ldb <PD.CYL+1,y Get # cylinders on drive (ignores high byte)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1283 lda <PD.SID,y Get # sides
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1284 mul Calculate # tracks on drive (1 per head)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1285 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1286 decd Adjust to ignore track 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1287 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1288 subd #$0001
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1289 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1290 lda <PD.SCT+1,y Get # sectors/track
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1291 sta DD.TKS,x Save in drive table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1292 sta <DD.SPT+1,x Save in other copy in drive table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1293 mul Calculate # sectors on drive (minus track 0)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1294 pshs x Preserve drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1295 tfr d,x Move # sectors on drive to X
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1296 lda <PD.T0S+1,y Get # sectors on track 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1297 leax a,x Add that many sectors to total
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1298 lda <PD.TYP,y Get device type settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1299 anda #%00000100 Mask out all but 512 byte sector flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1300 beq L0550 Not 512 byte sector, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1301 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1302 addr x,x Multiply by 2 (convert to 256 byte OS9 sectors)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1303 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1304 tfr x,d
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1305 leax d,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1306 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1307 L0550 tfr x,d Move # sectors to D
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1308 puls x Get back drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1309 std DD.TOT+1,x Save # sectors allowed on drive
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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diff changeset
1310 lda #UPDAT.+EXEC. Owner's read/write/exec attributes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1311 sta DD.ATT,x Set attributes for disk
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1312 lda <PD.DNS,y Get density settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1313 lsla Shift for DD.FMT
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1314 pshs a Preserve it a sec
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1315 lda <PD.SID,y Get # sides
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1316 deca Adjust to base 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1317 ora ,s+ Merge with density settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1318 sta <DD.FMT,x Save in device table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1319 clrb No error?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1320 puls pc,x Restore original LSN & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1321
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1322 emod
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1323 eom equ *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1324 end
ec6fb5543b22 Robert Gault's modifications for correcting timing errors
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parents: 1620
diff changeset
1325