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comparison level1/modules/boot_1773.asm @ 1520:5ff76789bec2

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Updated boot_1773.asm from Rodney H. sysgo.asm startup time now reflects release date.
author boisy
date Tue, 17 Feb 2004 22:46:06 +0000
parents 9a9734ef451c
children d669aab7d6d8
comparison
equal deleted inserted replaced
1519:e54480a359e4 1520:5ff76789bec2
17 * Added '.' output for each sector for OS-9 L2 and NitrOS9 for 17 * Added '.' output for each sector for OS-9 L2 and NitrOS9 for
18 * Mark Marlette (a special request :). 18 * Mark Marlette (a special request :).
19 * 19 *
20 * 6r3 2003/08/31 Robert Gault 20 * 6r3 2003/08/31 Robert Gault
21 * Put BLOB-stop code in place, changed orb #$30 to orb #$28 21 * Put BLOB-stop code in place, changed orb #$30 to orb #$28
22 *
23 * 6r4 2004/02/17 Rodney Hamilton
24 * Minor optimizations, improvements in source comments
22 25
23 nam Boot 26 nam Boot
24 ttl WD1773 Boot module 27 ttl WD1773 Boot module
25 28
26 IFP1 29 IFP1
27 use defsfile 30 use defsfile
28 use rbfdefs 31 use rbfdefs
29 ENDC 32 ENDC
30 33
31 * Drive select bits at $FF40 34 * FDC Control Register bits at $FF40
32 SIDESEL equ %01000000 35 HALTENA equ %10000000
33 DRVSEL2 equ %00100000 36 SIDESEL equ %01000000 DRVSEL3 if no DS drives
37 DDEN equ %00100000
38 READY equ %00010000 READY for Tandy WD1773-based controllers
34 MOTON equ %00001000 39 MOTON equ %00001000
35 PRECOMP equ %00000100 40 DRVSEL2 equ %00000100
36 DRVSEL1 equ %00000010 41 DRVSEL1 equ %00000010
37 DRVSEL0 equ %00000001 42 DRVSEL0 equ %00000001
38 43
39 * WD17x3 Definitions 44 * Default Boot Drive is /d0
40 CMDREG equ 8+0 45 BootDr set DRVSEL0
41 STATREG equ CMDREG 46
47 * WD17x3 DPort offsets
48 CONTROL equ 0
49 CMDREG equ 8+0 write-only
50 STATREG equ CMDREG read-only
42 TRACKREG equ 8+1 51 TRACKREG equ 8+1
43 SECTREG equ 8+2 52 SECTREG equ 8+2
44 DATAREG equ 8+3 53 DATAREG equ 8+3
45 54
46 * Sector Size 55 * Sector Size
47 SECTSIZE equ 256 56 SECTSIZE equ 256
48 57
49 58 * Step Rates:
50 * Step Rate: 59 * $00 = 6ms
51 * $00 = 6ms 60 * $01 = 12ms
52 * $01 = 61 * $02 = 20ms
53 * $02 = 62 * $03 = 30ms
54 * $03 = 30ms
55 STEP set $00 63 STEP set $00
56
57 *Drive value & number
58 * $01 = 0
59 * $02 = 1
60 * $03 = 2
61 BootDr set $01
62 64
63 tylg set Systm+Objct 65 tylg set Systm+Objct
64 atrv set ReEnt+rev 66 atrv set ReEnt+rev
65 rev set $03 67 rev set $04
66 edition set 6 68 edition set 6
67 69
68 mod eom,name,tylg,atrv,start,size 70 mod eom,name,tylg,atrv,start,size
69 71
72 * NOTE: these are U-stack offsets, not DP
70 drvsel rmb 1 73 drvsel rmb 1
71 buffptr rmb 2 74 buffptr rmb 2
72 currtrak rmb 1 75 currtrak rmb 1
73 *ddfmt rmb 1 76 *ddfmt rmb 1
74 ddtks rmb 1 no. of sectors per track 77 ddtks rmb 1 no. of sectors per track
75 *ddtot rmb 1 78 *ddtot rmb 1
76 dblsided rmb 1 79 dblsided rmb 1
77 side rmb 1 80 side rmb 1 side 2 flag
78 size equ . 81 size equ .
79 82
80 name fcs /Boot/ 83 name fcs /Boot/
81 fcb edition 84 fcb edition
82 85
87 bne MakeStak until we've created our stack 90 bne MakeStak until we've created our stack
88 91
89 tfr s,u put 'stack statics' in U 92 tfr s,u put 'stack statics' in U
90 * ldx #DPort 93 * ldx #DPort
91 lda #%11010000 ($D0) Force Interrupt (stops any command in progress) 94 lda #%11010000 ($D0) Force Interrupt (stops any command in progress)
92 sta DPort+CMDREG write command to command register 95 sta >DPort+CMDREG write command to command register
93 * sta CMDREG,x write command to command register 96 * sta CMDREG,x write command to command register
94 lbsr Delay2 delay a bit 97 lbsr Delay2 delay 54~
95 lda DPort+STATREG read status register 98 lda >DPort+STATREG clear status register
96 * lda STATREG,x read status register 99 * lda STATREG,x read status register
97 lda #$FF 100 lda #$FF
98 sta currtrak,u set current track to 255 101 sta currtrak,u set current track to 255
99 leax >NMIRtn,pcr point to NMI routine 102 leax >NMIRtn,pcr point to NMI routine
100 IFGT Level-1 103 IFGT Level-1
103 stx >D.XNMI+1 save address 106 stx >D.XNMI+1 save address
104 lda #$7E 107 lda #$7E
105 sta >D.XNMI 108 sta >D.XNMI
106 ENDC 109 ENDC
107 lda #MOTON+BootDr turn on drive motor 110 lda #MOTON+BootDr turn on drive motor
108 sta >DPort 111 sta >DPort+CONTROL
109 112
110 * delay loop to allow disk to spin up 113 * MOTOR ON spin-up delay loop (~307 mSec)
111 IFGT Level-1 114 IFGT Level-1
112 ldd #$C350 115 ldd #50000
113 ELSE 116 ELSE
114 ldd #$61A8 117 ldd #25000
115 ENDC 118 ENDC
116 IFNE H6309 119 IFNE H6309
117 nop 120 nop
118 ENDC 121 ENDC
119 L003A nop 122 L003A nop
142 bcs L00AA branch if error 145 bcs L00AA branch if error
143 146
144 * From LSN0, we get various pieces of info. 147 * From LSN0, we get various pieces of info.
145 * ldd DD.TOT+1,y 148 * ldd DD.TOT+1,y
146 * std ddtot,u 149 * std ddtot,u
147 lda <DD.FMT,y get format byte of LSN0 150 lda <DD.FMT,y get format byte of LSN0
148 * sta ddfmt,u save it for ??? 151 * sta ddfmt,u save it for ???
149 anda #FMT.SIDE keep side bit 152 anda #FMT.SIDE keep side bit
150 sta dblsided,u and save it 153 sta dblsided,u and save it
151 lda DD.TKS,y get sectors per track 154 lda DD.TKS,y get sectors per track
152 sta ddtks,u and save 155 sta ddtks,u and save
153 ldd <DD.BSZ,y get bootfile size 156 ldd <DD.BSZ,y get bootfile size
154 std ,s save on stack 157 std ,s save on stack
155 ldx <DD.BT+1,y get start sector of bootfile 158 ldx <DD.BT+1,y get start sector of bootfile
156 pshs x push on the stack 159 pshs x push on the stack
157 ldd #SECTSIZE load D with sector size 160 ldd #SECTSIZE load D with sector size
158 ldu buffptr,u and point to the buffer pointer 161 ldu buffptr,u and point to the buffer pointer
159 os9 F$SRtMem return the memory 162 os9 F$SRtMem return the memory
160 ldd $02,s get the bootfile size 163 ldd $02,s get the bootfile size
161 IFGT Level-1 164 IFGT Level-1
162 os9 F$BtMem 165 os9 F$BtMem
163 ELSE 166 ELSE
164 os9 F$SRqMem get the memory from the system 167 os9 F$SRqMem get the memory from the system
165 ENDC 168 ENDC
166 puls x pull bootfile start sector off stack 169 puls x pull bootfile start sector off stack
167 bcs L00AA branch if error 170 bcs L00AA branch if error
168 stu $02,s save pointer to bootfile mem on stack 171 stu 2,s save pointer to bootfile mem on stack
169 tfr u,d transfer to D for later store 172 stu 8+buffptr,s also save to buffptr,u
170 ldu $06,s restore original U 173 ldu 6,s reload original U
171 * ldd $02,s get pointer to bootfile mem 174 * ldd 2,s get pointer to bootfile mem
172 std buffptr,u and save pointer 175 * std buffptr,u and save pointer
173 ldd ,s get bootfile size 176 ldd ,s get bootfile size
174 beq L00A3 branch if zero 177 beq L00A3 branch if zero
175 178
176 * this loop reads a sector at a time from the bootfile 179 * this loop reads a sector at a time from the bootfile
177 * X = start sector 180 * X = start sector
178 * D = bootfile size 181 * D = bootfile size
179 L0091 pshs x,b,a save params 182 L0091 pshs x,b,a save params
180 clrb 183 clrb
181 bsr ReadSect read sector 184 bsr ReadSect read sector
182 bcs L00A8 branch if error 185 bcs L00A8 branch if error
183 IFGT Level-1 186 IFGT Level-1
184 lda #'. dump out a period for boot debugging 187 lda #'. dump out a period for boot debugging
185 jsr <D.BtBug do the debug stuff 188 jsr <D.BtBug do the debug stuff
186 ENDC 189 ENDC
187 puls x,b,a get params 190 puls x,b,a restore params
188 inc buffptr,u point to next 256 bytes 191 * RVH NOTE: the next 3 lines assume sector size=256=LSN size?
189 leax 1,x move to next sector 192 inc buffptr,u point to next 256 bytes
190 subd #SECTSIZE subtract sector bytes from size 193 leax 1,x move to next sector
191 bhi L0091 continue if more space 194 subd #SECTSIZE subtract sector bytes from size
195 bhi L0091 continue if more space
192 L00A3 clrb 196 L00A3 clrb
193 puls b,a 197 puls b,a
194 bra L00AC 198 bra L00AC
195 L00A8 leas $04,s 199 L00A8 leas $04,s
196 L00AA leas $02,s 200 L00AA leas $02,s
197 L00AC puls u,y,x 201 L00AC puls u,y,x
198 leas size,s clean up stack 202 leas size,s clean up stack
199 clr >DPort shut off floppy disk 203 clr >DPort+CONTROL shut off floppy disk
200 rts 204 rts
201 205
202 L00B7 lda #DRVSEL2+MOTON+BootDr permit alternate drives 206 L00B7 lda #DDEN+MOTON+BootDr permit alternate drives
203 sta drvsel,u save drive selection byte 207 sta drvsel,u save drive selection byte
204 clr currtrak,u clear current track 208 clr currtrak,u clear current track
205 lda #$05 209 lda #$05
206 lbsr L0170 210 lbsr L0170
207 ldb #STEP 211 ldb #0+STEP RESTORE cmd
208 lbra L0195 212 lbra L0195
209 213
210 * Read a sector from the 1773 214 * Read a sector from the 1773
211 * Entry: X = LSN to read 215 * Entry: X = LSN to read
212 ReadSect lda #$91 216 ReadSect lda #$91
222 pshs x,b,a 226 pshs x,b,a
223 bsr L00B7 227 bsr L00B7
224 puls x,b,a 228 puls x,b,a
225 L00DF pshs x,b,a save LSN, command 229 L00DF pshs x,b,a save LSN, command
226 bsr L00EA 230 bsr L00EA
227 puls x,b,a get LSN, command 231 puls x,b,a restore LSN, command
228 bcc L00D6 branch if OK 232 bcc L00D6 branch if OK
229 lsra 233 lsra
230 bne L00D7 234 bne L00D7
231 L00EA bsr L013C 235 L00EA bsr L013C
232 bcs L00D6 if error, return to caller 236 bcs L00D6 if error, return to caller
234 orcc #IntMasks mask interrupts 238 orcc #IntMasks mask interrupts
235 pshs y save Y 239 pshs y save Y
236 ldy #$FFFF 240 ldy #$FFFF
237 ldb #%10000000 ($80) READ SECTOR command 241 ldb #%10000000 ($80) READ SECTOR command
238 stb >DPort+CMDREG write to command register 242 stb >DPort+CMDREG write to command register
239 ldb drvsel,u 243 ldb drvsel,u (DDEN+MOTORON+BootDr)
240 * Notes on the next line: 244 * NOTE: The 1773 FDC multiplexes the write precomp enable and ready
241 * The byte in question comes after telling the controller that it should 245 * signals on the ENP/RDY pin, so the READY bit must always be ON for
242 * read a sector. RegB is then loaded (ldb drvsel,u) which means it is set to $29 246 * read and seek commands. (from the FD502 FDC Service Manual)
243 * (%00101001) or the default boot drive if sub L00B7 has been run. At this 247 orb #DDEN+READY set DDEN+READY bits ($30)
244 * point an orb #$30 or orb #%00110000 means that write precomp and double 248 tst side,u are we on side 2?
245 * density flags are or'd in. This does not make any sense at all for a
246 * read command. I suppose the command may not even be needed but $28 just
247 * ensures that motor on and double density are set.
248 * orb #$28 was $30 which RG thinks is an error
249 * 09/02/03: Futher investigation shows that the OS-9 Level One Booter will
250 * FAIL if orb #$28 is used. It does not fail if orb #$30 is used. ????
251 orb #$30 RG thinks is an error
252 tst side,u
253 beq L0107 249 beq L0107
254 orb #SIDESEL 250 orb #SIDESEL set side 2 bit
255 L0107 stb >DPort 251 L0107 stb >DPort+CONTROL
256 lbsr Delay2 252 lbsr Delay2 delay 54~
257 orb #$80 253 orb #HALTENA HALT enable ($80)
258 * lda #%00000010 ($02) RESTORE 254 * lda #%00000010 RESTORE cmd ($02)
259 *L0111 bita >DPort+STATREG 255 *L0111 bita >DPort+STATREG
260 * bne L0123 256 * bne L0123
261 * leay -$01,y 257 * leay -$01,y
262 * bne L0111 258 * bne L0111
263 * lda drvsel,u 259 * lda drvsel,u
264 * sta >DPort 260 * sta >DPort+CONTROL
265 * puls y 261 * puls y
266 * bra L0138 262 * bra L0138
267 stb >DPort 263 stb >DPort+CONTROL
268 nop 264 nop
269 nop 265 nop
270 bra L0123 266 bra L0123
271 267
272 * Sector READ Loop 268 * Sector READ Loop
273 L0123 lda >DPort+DATAREG read from WD DATA register 269 L0123 lda >DPort+DATAREG read from WD DATA register
274 sta ,x+ 270 sta ,x+
275 * stb >DPort 271 * stb >DPort+CONTROL
276 nop 272 nop
277 bra L0123 273 bra L0123
274 * RVH NOTE: This ONLY works for double density boot disks! The Tandy
275 * controllers internally gate HALT enable with the DDEN bit, which
276 * means that reading a single-density boot disk will not generate the
277 * NMI signal needed to exit the read loop! Single-density disks must
278 * use a polled I/O loop instead.
278 279
279 NMIRtn leas R$Size,s adjust stack 280 NMIRtn leas R$Size,s adjust stack
280 puls y 281 puls y
281 ldb >DPort+STATREG read WD STATUS register 282 ldb >DPort+STATREG read WD STATUS register
282 bitb #$9C any errors? 283 bitb #$9C any errors?
287 ldb #E$Read 288 ldb #E$Read
288 RetOK rts 289 RetOK rts
289 290
290 L013C lda #MOTON+BootDr permit alternate drives 291 L013C lda #MOTON+BootDr permit alternate drives
291 sta drvsel,u save byte to static mem 292 sta drvsel,u save byte to static mem
292 clr side,u assume side 0 293 clr side,u start on side 1
293 tfr x,d 294 tfr x,d
294 cmpd #$0000 295 cmpd #$0000
295 beq L016C 296 beq L016C
296 clr ,-s clear space on stack 297 clr ,-s clear space on stack
297 tst dblsided,u disk double sided? 298 tst dblsided,u double sided disk?
298 beq L0162 branch if not 299 beq L0162 branch if not
299 bra L0158 300 bra L0158
300 * Double-sided code 301 * Double-sided code
301 L0152 com side,u 302 L0152 com side,u flag side 2
302 bne L0158 303 bne L0158
303 inc ,s 304 inc ,s
304 L0158 subb ddtks,u 305 L0158 subb ddtks,u
305 sbca #$00 306 sbca #$00
306 bcc L0152 307 bcc L0152
313 puls a get current track indicator off of stack 314 puls a get current track indicator off of stack
314 L016C incb 315 L016C incb
315 stb >DPort+SECTREG save in sector register 316 stb >DPort+SECTREG save in sector register
316 L0170 ldb currtrak,u get current track in B 317 L0170 ldb currtrak,u get current track in B
317 stb >DPort+TRACKREG save in track register 318 stb >DPort+TRACKREG save in track register
318 cmpa currtrak,u same as A 319 cmpa currtrak,u same as A?
319 beq L018D branch if so 320 beq L018D branch if so
320 sta currtrak,u 321 sta currtrak,u
321 sta >DPort+DATAREG 322 sta >DPort+DATAREG
322 ldb #$10+STEP SEEK command 323 ldb #$10+STEP SEEK command
323 bsr L0195 send command to controller 324 bsr L0195 send command to controller
324 pshs x 325 pshs x
325 * Delay 326 * Seek Delay
326 ldx #$222E 327 ldx #$222E delay ~39 mSec (78mS L1)
327 L0187 leax -$01,x 328 L0187 leax -$01,x
328 bne L0187 329 bne L0187
329 puls x 330 puls x
330 L018D clrb 331 L018D clrb
331 rts 332 rts
333 *ChkErr bitb #$98 evaluate WD status (READY, RNF, CRC err) 334 *ChkErr bitb #$98 evaluate WD status (READY, RNF, CRC err)
334 * bne L0138 335 * bne L0138
335 * clrb 336 * clrb
336 * rts 337 * rts
337 338
338 L0195 bsr Delay1 339 L0195 bsr L01A8 issue FDC cmd, wait 54~
339 L0197 ldb >DPort+STATREG 340 L0197 ldb >DPort+STATREG
340 bitb #$01 341 bitb #$01 still BUSY?
341 bne L0197 342 bne L0197 loop until command completes
342 rts 343 rts
343 344
344 * Entry: B = command byte 345 * Entry: B = command byte
345 L019F lda drvsel,u 346 L019F lda drvsel,u
346 sta >DPort 347 sta >DPort+CONTROL
347 stb >DPort+CMDREG 348 stb >DPort+CMDREG
348 rts 349 rts
349 350
351 * issue command and wait 54 clocks
352 * Controller requires a min delay of 14uS (DD) or 28uS (SD)
353 * following a command write before status register is valid
354 L01A8
355 bsr L019F
350 * Delay branches 356 * Delay branches
351 Delay1 357 * 54 clock delay including bsr (=30uS/L2,60us/L1)
352 IFNE H6309
353 nop
354 ENDC
355 bsr L019F
356 Delay2 358 Delay2
357 IFNE H6309 359 IFNE H6309
358 nop 360 nop
359 nop 361 nop
360 ENDC 362 ENDC
377 ENDC 379 ENDC
378 380
379 emod 381 emod
380 eom equ * 382 eom equ *
381 end 383 end
382