comparison level1/modules/clock.asm @ 1945:89bba8b61def

Level 1 slow time update bug fixed
author boisy
date Mon, 05 Dec 2005 01:15:10 +0000
parents 8234be91628d
children d88e7ec829a5
comparison
equal deleted inserted replaced
1944:c40f6a2fdeb6 1945:89bba8b61def
35 * will disable the IRQ from them, this is ok for Level 2/CoCo 3 as the 35 * will disable the IRQ from them, this is ok for Level 2/CoCo 3 as the
36 * IRQ is later enabled from the GIME, however the CoCo 1,2 and Dragon 36 * IRQ is later enabled from the GIME, however the CoCo 1,2 and Dragon
37 * do not posses a GIME so anything dependent on the clock tick will 37 * do not posses a GIME so anything dependent on the clock tick will
38 * hang. So changed to conditionaly compile based on level :- 38 * hang. So changed to conditionaly compile based on level :-
39 * 39 *
40 * Level 1 $3435 40 * 9r8 2005/12/04 Boisy G. Pitre
41 * Level 2 $3434 41 * Minor code optimizations, fixed issue in Level 1 where clock ran slow
42 * 42 * due to improper initialization of certain system globals.
43 43
44 nam Clock 44 nam Clock
45 ttl NitrOS-9 System Clock 45 ttl NitrOS-9 System Clock
46 46
47 ifp1 47 ifp1
48 use defsfile 48 use defsfile
51 endc 51 endc
52 endc 52 endc
53 53
54 tylg set Systm+Objct 54 tylg set Systm+Objct
55 atrv set ReEnt+rev 55 atrv set ReEnt+rev
56 rev set 7 56 rev set 8
57 edition set 9 57 edition set 9
58 58
59 59
60 *------------------------------------------------------------ 60 *------------------------------------------------------------
61 * 61 *
114 std <D.Min 114 std <D.Min
115 endc 115 endc
116 lda #TkPerSec reset to start of second 116 lda #TkPerSec reset to start of second
117 sta <D.Tick 117 sta <D.Tick
118 ldx <D.Clock2 get entry point to Clock2 118 ldx <D.Clock2 get entry point to Clock2
119 clra clear carry
119 jmp $06,x and call SetTime entry point 120 jmp $06,x and call SetTime entry point
120 121
121 122
122 *-------------------------------------------------- 123 *--------------------------------------------------
123 * 124 *
203 lda ,x clear possible pending PIA0 HBORD IRQ 204 lda ,x clear possible pending PIA0 HBORD IRQ
204 endc 205 endc
205 lda 2,x clear possible pending PIA0 VBORD IRQ 206 lda 2,x clear possible pending PIA0 VBORD IRQ
206 207
207 * Don't need to explicitly read RTC during initialization 208 * Don't need to explicitly read RTC during initialization
208 ldd #59*256+TkPerTS last second and time slice in minute 209 ldd #59*256+$01 last second and last tick
209 std <D.Sec will prompt RTC read at next time slice 210 std <D.Sec will prompt RTC read at next time slice
211 ifeq Level-1
212 ldb #TkPerSec
213 stb <D.TSec set ticks per second
214 endc
215 ldb #TkPerTS get ticks per time slice
210 stb <D.TSlice set ticks per time slice 216 stb <D.TSlice set ticks per time slice
211 stb <D.Slice set first time slice 217 stb <D.Slice set first time slice
212 leax SvcIRQ,pcr set IRQ handler 218 leax SvcIRQ,pcr set IRQ handler
213 stx <D.IRQ 219 stx <D.IRQ
214 220
238 244
239 ifeq Level-1 245 ifeq Level-1
240 * 246 *
241 * Clock IRQ Entry Point 247 * Clock IRQ Entry Point
242 * 248 *
243 * Called once every 1.66666ms 249 * For CoCo 1/2, called once every 16.667 milliseconds
244 SvcIRQ 250 SvcIRQ
245 clra 251 clra
246 tfr a,dp set direct page to zero 252 tfr a,dp set direct page to zero
247 lda PIA0Base+3 get hw byte 253 tst PIA0Base+3 get hw byte
248 bmi L0032 branch if sync flag on 254 bmi L0032 branch if sync flag on
249 jmp [>D.SvcIRQ] else service other possible IRQ 255 jmp [>D.SvcIRQ] else service other possible IRQ
250 L0032 lda PIA0Base+2 clear interrupt 256 L0032 tst PIA0Base+2 clear interrupt
251 dec <D.Tick decrement tick counter 257 dec <D.Tick decrement tick counter
252 bne L007F go around if not zero 258 bne L007F go around if not zero
253 ldb <D.Sec get minutes/seconds 259 ldb <D.Sec get minutes/seconds
254 * Seconds increment 260 * Seconds increment
255 incb increment seconds 261 incb increment seconds