comparison level2/coco3/modules/makefile @ 2868:cfa46960b6bd

makefiles: Rename DW3 to DW all over Rename dw3*.sb to dwio*.sb This is part of getting default and lwtools-port branches together, trying to avoid things falling through the cracks.
author Tormod Volden <debian.tormod@gmail.com>
date Sun, 24 Nov 2013 11:13:40 +0100
parents e4a0f58a5f9b
children cfa6222348f7
comparison
equal deleted inserted replaced
2867:97ba1059a8ce 2868:cfa46960b6bd
23 23
24 DEPENDS = ./makefile 24 DEPENDS = ./makefile
25 TPB = $(3RDPARTY)/booters 25 TPB = $(3RDPARTY)/booters
26 26
27 BOOTERS = boot_1773_6ms boot_1773_30ms \ 27 BOOTERS = boot_1773_6ms boot_1773_30ms \
28 boot_burke boot_rampak boot_wd1002 boot_dw3 boot_dw3_becker \ 28 boot_burke boot_rampak boot_wd1002 boot_dw boot_dw_becker \
29 boot_tc3 boot_ide boot_rom 29 boot_tc3 boot_ide boot_rom
30 BOOTTRACK = rel_32 rel_40 rel_80 rel_32_50hz rel_40_50hz rel_80_50hz $(BOOTERS) krn 30 BOOTTRACK = rel_32 rel_40 rel_80 rel_32_50hz rel_40_50hz rel_80_50hz $(BOOTERS) krn
31 KERNEL = krnp2 krnp3_perr krnp4_regdump 31 KERNEL = krnp2 krnp3_perr krnp4_regdump
32 SYSMODS = ioman init sysgo_h0 sysgo_dd sysgo_rom rominfo vectors 32 SYSMODS = ioman init sysgo_h0 sysgo_dd sysgo_rom rominfo vectors
33 CLOCKS = clock_60hz clock_50hz \ 33 CLOCKS = clock_60hz clock_50hz \
34 clock2_elim clock2_disto2 clock2_disto4 clock2_bnb \ 34 clock2_elim clock2_disto2 clock2_disto4 clock2_bnb \
35 clock2_smart clock2_harris clock2_cloud9 clock2_soft \ 35 clock2_smart clock2_harris clock2_cloud9 clock2_soft \
36 clock2_jvemu clock2_messemu clock2_dw3 clock2_dw3_becker 36 clock2_jvemu clock2_messemu clock2_dw clock2_dw_becker
37 37
38 RBF = rbf.mn \ 38 RBF = rbf.mn \
39 rbdw3.dr dw3.sb dw3_becker.sb \ 39 rbdw.dr dwio.sb dwio_becker.sb \
40 rb1773.dr rb1773_scii_ff74.dr rb1773_scii_ff58.dr \ 40 rb1773.dr rb1773_scii_ff74.dr rb1773_scii_ff58.dr \
41 d0_35s.dd d1_35s.dd d2_35s.dd d3_35s.dd \ 41 d0_35s.dd d1_35s.dd d2_35s.dd d3_35s.dd \
42 d0_40d.dd d1_40d.dd d2_40d.dd d0_80d.dd \ 42 d0_40d.dd d1_40d.dd d2_40d.dd d0_80d.dd \
43 d1_80d.dd d2_80d.dd \ 43 d1_80d.dd d2_80d.dd \
44 ddd0_35s.dd ddd0_40d.dd ddd0_80d.dd \ 44 ddd0_35s.dd ddd0_40d.dd ddd0_80d.dd \
113 # SuperIDE/Glenside IDE Booter 113 # SuperIDE/Glenside IDE Booter
114 boot_ide: boot_ide.asm 114 boot_ide: boot_ide.asm
115 $(AS) $(ASOUT)$@ $< $(IDEFLAGS) 115 $(AS) $(ASOUT)$@ $< $(IDEFLAGS)
116 116
117 # DriveWire 3 Becker Booter 117 # DriveWire 3 Becker Booter
118 boot_dw3_becker: boot_dw3.asm 118 boot_dw_becker: boot_dw.asm
119 $(AS) $< $(ASOUT)$@ $(AFLAGS) -aBECKER=1 119 $(AS) $< $(ASOUT)$@ $(AFLAGS) -aBECKER=1
120 120
121 # DriveWire 3 Becker Submodule 121 # DriveWire 3 Becker Submodule
122 dw3_becker.sb: dw3.asm 122 dwio_becker.sb: dw.asm
123 $(AS) $< $(ASOUT)$@ $(AFLAGS) -aBECKER=1 123 $(AS) $< $(ASOUT)$@ $(AFLAGS) -aBECKER=1
124 124
125 # CoGrf/CoVDG Modules 125 # CoGrf/CoVDG Modules
126 cogrf.io: cowin.asm 126 cogrf.io: cowin.asm
127 $(AS) $< $(ASOUT)$@ $(AFLAGS) -aCoGrf=1 127 $(AS) $< $(ASOUT)$@ $(AFLAGS) -aCoGrf=1
412 $(AS) $(AFLAGS) $(ASOUT)$@ $< -aCLOUD9=1 412 $(AS) $(AFLAGS) $(ASOUT)$@ $< -aCLOUD9=1
413 413
414 clock2_bnb: clock2_ds1315.asm 414 clock2_bnb: clock2_ds1315.asm
415 $(AS) $(AFLAGS) $(ASOUT)$@ $< -aBNB=1 415 $(AS) $(AFLAGS) $(ASOUT)$@ $< -aBNB=1
416 416
417 clock2_dw3_becker: clock2_dw3.asm 417 clock2_dw_becker: clock2_dw.asm
418 $(AS) $(AFLAGS) $(ASOUT)$@ $< -aBECKER=1 418 $(AS) $(AFLAGS) $(ASOUT)$@ $< -aBECKER=1
419 419
420 clean: 420 clean:
421 $(CD) kernel; make $@ 421 $(CD) kernel; make $@
422 $(RM) $(ALLOBJS) 422 $(RM) $(ALLOBJS)