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comparison level2/coco3/bootfiles/makefile @ 3151:d5c884d63e53

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coco3fpga: Build boot files and disk images with RAM disk and RTC support Amend "coco3/bootfiles/makefile" to make bootfiles including "ramd_coco3fpga.dr", "r0_ramd_coco3fpga.dd", & "clock2_coco3fpga" Added two new disks to the "coco3fpga/makefile" disk definitions for bootdisks supporting the Coco3FPGA ramdisk and RTC.
author Bill Pierce <merlinious999@gmail.com>
date Mon, 06 Feb 2017 22:25:15 +0100
parents 0413a77a3686
children adc28092355b
comparison
equal deleted inserted replaced
3150:37737e5ec640 3151:d5c884d63e53
52 RBDWARDUINO = $(MD)/rbdw.dr $(MD)/dwio_arduino.sb \ 52 RBDWARDUINO = $(MD)/rbdw.dr $(MD)/dwio_arduino.sb \
53 $(MD)/x1.dd $(MD)/x2.dd $(MD)/x3.dd 53 $(MD)/x1.dd $(MD)/x2.dd $(MD)/x3.dd
54 RBDWBECKER = $(MD)/rbdw.dr $(MD)/dwio_becker.sb \ 54 RBDWBECKER = $(MD)/rbdw.dr $(MD)/dwio_becker.sb \
55 $(MD)/x1.dd $(MD)/x2.dd $(MD)/x3.dd 55 $(MD)/x1.dd $(MD)/x2.dd $(MD)/x3.dd
56 RBCOCO3FPGA = $(MD)/rbsuper.dr $(MD)/llcoco3fpga.dr \ 56 RBCOCO3FPGA = $(MD)/rbsuper.dr $(MD)/llcoco3fpga.dr \
57 $(MD)/sd1_coco3fpga.dd 57 $(MD)/sd1_coco3fpga.dd $(MD)/ramd_coco3fpga.dr \
58 $(MD)/r0_ramd_coco3fpga.dd
58 59
59 SCDWV_NET = $(MD)/n_scdwv.dd $(MD)/n1_scdwv.dd $(MD)/n2_scdwv.dd \ 60 SCDWV_NET = $(MD)/n_scdwv.dd $(MD)/n1_scdwv.dd $(MD)/n2_scdwv.dd \
60 $(MD)/n3_scdwv.dd $(MD)/n4_scdwv.dd $(MD)/n5_scdwv.dd \ 61 $(MD)/n3_scdwv.dd $(MD)/n4_scdwv.dd $(MD)/n5_scdwv.dd \
61 $(MD)/n6_scdwv.dd $(MD)/n7_scdwv.dd $(MD)/n8_scdwv.dd \ 62 $(MD)/n6_scdwv.dd $(MD)/n7_scdwv.dd $(MD)/n8_scdwv.dd \
62 $(MD)/n9_scdwv.dd $(MD)/n10_scdwv.dd $(MD)/n11_scdwv.dd \ 63 $(MD)/n9_scdwv.dd $(MD)/n10_scdwv.dd $(MD)/n11_scdwv.dd \
67 SCDWP = $(MD)/scdwp.dr $(MD)/p_scdwp.dd 68 SCDWP = $(MD)/scdwp.dr $(MD)/p_scdwp.dd
68 PIPE = $(MD)/pipeman.mn $(MD)/piper.dr $(MD)/pipe.dd 69 PIPE = $(MD)/pipeman.mn $(MD)/piper.dr $(MD)/pipe.dd
69 CLOCK50HZ = $(MD)/clock_50hz $(MD)/clock2_soft 70 CLOCK50HZ = $(MD)/clock_50hz $(MD)/clock2_soft
70 CLOCK60HZ = $(MD)/clock_60hz $(MD)/clock2_soft 71 CLOCK60HZ = $(MD)/clock_60hz $(MD)/clock2_soft
71 CLOCK60HZDW = $(MD)/clock_60hz $(MD)/clock2_dw 72 CLOCK60HZDW = $(MD)/clock_60hz $(MD)/clock2_dw
73 CLOCK60HZCC3FPGA = $(MD)/clock_60hz $(MD)/clock2_coco3fpga
72 74
73 # NitrOS-9 disk bootfile to allow booting from DriveWire server 75 # NitrOS-9 disk bootfile to allow booting from DriveWire server
74 # on a DE1 or Xilinx using Gary Becker's CoCo 3 FGPA 76 # on a DE1 or Xilinx using Gary Becker's CoCo 3 FGPA
75 BOOTFILE_COCO3FPGA = $(MD)/krnp2 $(MD)/ioman $(MD)/init \ 77 BOOTFILE_COCO3FPGA = $(MD)/krnp2 $(MD)/ioman $(MD)/init \
76 $(MD)/rbf.mn \ 78 $(MD)/rbf.mn \
100 $(SCDWV_WIN) \ 102 $(SCDWV_WIN) \
101 $(SCDWP) \ 103 $(SCDWP) \
102 $(PIPE) \ 104 $(PIPE) \
103 $(CLOCK60HZDW) 105 $(CLOCK60HZDW)
104 106
107 BOOTFILE_COCO3FPGA_SD_RTC = $(MD)/krnp2 $(MD)/ioman $(MD)/init \
108 $(MD)/rbf.mn \
109 $(RBDWBECKER) \
110 $(MD)/x0.dd \
111 $(RBCOCO3FPGA) \
112 $(MD)/ddsd0_coco3fpga.dd\
113 $(MD)/scf.mn \
114 $(VTIO_COWIN_80) \
115 $(MD)/scdwv.dr \
116 $(SCDWV_NET) \
117 $(SCDWV_WIN) \
118 $(SCDWP) \
119 $(PIPE) \
120 $(CLOCK60HZCC3FPGA)
121
105 BOOTFILE_COCO3FPGA_ROM = $(MD)/krnp2 $(MD)/ioman $(MD)/init \ 122 BOOTFILE_COCO3FPGA_ROM = $(MD)/krnp2 $(MD)/ioman $(MD)/init \
106 $(MD)/rbf.mn \ 123 $(MD)/rbf.mn \
107 $(RBDWBECKER) \ 124 $(RBDWBECKER) \
108 $(MD)/x0.dd \ 125 $(MD)/x0.dd \
109 $(RBCOCO3FPGA) \ 126 $(RBCOCO3FPGA) \
129 $(SCDWV_NET) \ 146 $(SCDWV_NET) \
130 $(SCDWV_WIN) \ 147 $(SCDWV_WIN) \
131 $(SCDWP) \ 148 $(SCDWP) \
132 $(PIPE) \ 149 $(PIPE) \
133 $(CLOCK60HZDW) 150 $(CLOCK60HZDW)
151
152 BOOTFILE_COCO3FPGA_ROM_RTC = $(MD)/krnp2 $(MD)/ioman $(MD)/init \
153 $(MD)/rbf.mn \
154 $(RBDWBECKER) \
155 $(MD)/x0.dd \
156 $(RBCOCO3FPGA) \
157 $(MD)/ddsd0_coco3fpga.dd\
158 $(MD)/scf.mn \
159 $(VTIO_COWIN_80) \
160 $(MD)/scdwv.dr \
161 $(SCDWV_NET) \
162 $(SCDWV_WIN) \
163 $(SCDWP) \
164 $(PIPE) \
165 $(CLOCK60HZCC3FPGA)
134 166
135 BOOTFILE_BECKER = $(MD)/krnp2 $(MD)/ioman $(MD)/init \ 167 BOOTFILE_BECKER = $(MD)/krnp2 $(MD)/ioman $(MD)/init \
136 $(MD)/rbf.mn \ 168 $(MD)/rbf.mn \
137 $(RBDWBECKER) \ 169 $(RBDWBECKER) \
138 $(MD)/ddx0.dd \ 170 $(MD)/ddx0.dd \
286 318
287 BOOTFILES = bootfile_40d bootfile_40d_50hz bootfile_80d \ 319 BOOTFILES = bootfile_40d bootfile_40d_50hz bootfile_80d \
288 bootfile_80d_50hz bootfile_dw bootfile_dw_headless \ 320 bootfile_80d_50hz bootfile_dw bootfile_dw_headless \
289 bootfile_becker bootfile_arduino bootfile_becker_headless \ 321 bootfile_becker bootfile_arduino bootfile_becker_headless \
290 bootfile_arduino_headless bootfile_cocosdc bootfile_ide \ 322 bootfile_arduino_headless bootfile_cocosdc bootfile_ide \
291 bootfile_coco3fpga bootfile_coco3fpga_sd \ 323 bootfile_coco3fpga bootfile_coco3fpga_sd bootfile_coco3fpga_sd_rtc \
292 bootfile_coco3fpga_rom bootfile_coco3fpga_rom_dw 324 bootfile_coco3fpga_rom bootfile_coco3fpga_rom_dw bootfile_coco3fpga_rom_rtc
293 325
294 KERNELS = kernel_1773 kernel_1773_50hz kernel_dw kernel_becker \ 326 KERNELS = kernel_1773 kernel_1773_50hz kernel_dw kernel_becker \
295 kernel_arduino kernel_cocosdc kernel_ide kernel_dide 327 kernel_arduino kernel_cocosdc kernel_ide kernel_dide
296 328
297 ALLOBJS = $(BOOTFILES) $(KERNELS) 329 ALLOBJS = $(BOOTFILES) $(KERNELS)
303 $(MERGE) $(BOOTFILE_COCO3FPGA)>$@ 335 $(MERGE) $(BOOTFILE_COCO3FPGA)>$@
304 336
305 bootfile_coco3fpga_sd: $(BOOTFILE_COCO3FPGA_SD) $(DEPENDS) 337 bootfile_coco3fpga_sd: $(BOOTFILE_COCO3FPGA_SD) $(DEPENDS)
306 $(MERGE) $(BOOTFILE_COCO3FPGA_SD)>$@ 338 $(MERGE) $(BOOTFILE_COCO3FPGA_SD)>$@
307 339
340 bootfile_coco3fpga_sd_rtc: $(BOOTFILE_COCO3FPGA_SD_RTC) $(DEPENDS)
341 $(MERGE) $(BOOTFILE_COCO3FPGA_SD_RTC)>$@
342
308 bootfile_coco3fpga_rom: $(BOOTFILE_COCO3FPGA_ROM) $(DEPENDS) 343 bootfile_coco3fpga_rom: $(BOOTFILE_COCO3FPGA_ROM) $(DEPENDS)
309 $(MERGE) $(BOOTFILE_COCO3FPGA_ROM)>$@ 344 $(MERGE) $(BOOTFILE_COCO3FPGA_ROM)>$@
310 345
311 bootfile_coco3fpga_rom_dw: $(BOOTFILE_COCO3FPGA_ROM_DW) $(DEPENDS) 346 bootfile_coco3fpga_rom_dw: $(BOOTFILE_COCO3FPGA_ROM_DW) $(DEPENDS)
312 $(MERGE) $(BOOTFILE_COCO3FPGA_ROM_DW)>$@ 347 $(MERGE) $(BOOTFILE_COCO3FPGA_ROM_DW)>$@
348
349 bootfile_coco3fpga_rom_rtc: $(BOOTFILE_COCO3FPGA_ROM_RTC) $(DEPENDS)
350 $(MERGE) $(BOOTFILE_COCO3FPGA_ROM_RTC)>$@
313 351
314 bootfile_becker: $(BOOTFILE_BECKER) $(DEPENDS) 352 bootfile_becker: $(BOOTFILE_BECKER) $(DEPENDS)
315 $(MERGE) $(BOOTFILE_BECKER)>$@ 353 $(MERGE) $(BOOTFILE_BECKER)>$@
316 354
317 bootfile_arduino: $(BOOTFILE_ARDUINO) $(DEPENDS) 355 bootfile_arduino: $(BOOTFILE_ARDUINO) $(DEPENDS)