Mercurial > hg > Members > kono > nitros9-code

comparison defs/systype @ 2024:e396d4f24b27

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Ran each file through pretty print
author boisy
date Tue, 14 Mar 2006 12:20:57 +0000
parents 83453a4c9e51
children
comparison
equal deleted inserted replaced
2023:dbaeafb56535 2024:e396d4f24b27
1 IFNE SYSTYPE-1 1 IFNE SYSTYPE-1
2 2
3 SYSTYPE set 1 3 SYSTYPE SET 1
4 4
5 ******************************************************************** 5 ********************************************************************
6 * SysType - NitrOS-9 System Specific Definitions 6 * SysType - NitrOS-9 System Specific Definitions
7 * 7 *
8 * $Id$ 8 * $Id$
30 * Statics now are prefaced with V. to identify them easier in source. 30 * Statics now are prefaced with V. to identify them easier in source.
31 * 31 *
32 * 2004/07/18 Boisy G. Pitre 32 * 2004/07/18 Boisy G. Pitre
33 * Moved CoCo 3 Window stuff into cc3iodefs 33 * Moved CoCo 3 Window stuff into cc3iodefs
34 34
35 nam SysType 35 NAM SysType
36 IFEQ Level-1 36 IFEQ Level-1
37 ttl NitrOS-9 Level 1 System Type Definitions 37 TTL NitrOS-9 Level 1 System Type Definitions
38 ELSE 38 ELSE
39 IFEQ Level-2 39 IFEQ Level-2
40 ttl NitrOS-9 Level 2 System Type Definitions 40 TTL NitrOS-9 Level 2 System Type Definitions
41 ENDC 41 ENDC
42 IFEQ Level-3 42 IFEQ Level-3
43 ttl NitrOS-9 Level 3 System Type Definitions 43 TTL NitrOS-9 Level 3 System Type Definitions
44 ENDC 44 ENDC
45 ENDC 45 ENDC
46 46
47 47
48 ********************** 48 **********************
49 * CPU Type Definitions 49 * CPU Type Definitions
50 * 50 *
51 Color set 1 51 Color SET 1
52 Color3 set 2 52 Color3 SET 2
53 IFEQ Level-1 53 IFEQ Level-1
54 CPUType set Color 54 CPUType SET Color
55 ELSE 55 ELSE
56 CPUType set Color3 56 CPUType SET Color3
57 ENDC 57 ENDC
58 58
59 59
60 ****************************** 60 ******************************
61 * Clock Speed Type Definitions 61 * Clock Speed Type Definitions
62 * 62 *
63 OneMHz equ 1 63 OneMHz EQU 1
64 TwoMHz equ 2 64 TwoMHz EQU 2
65 IFEQ CPUType-Color 65 IFEQ CPUType-Color
66 CPUSpeed set OneMHz 66 CPUSpeed SET OneMHz
67 ELSE 67 ELSE
68 CPUSpeed set TwoMHz 68 CPUSpeed SET TwoMHz
69 ENDC 69 ENDC
70 70
71 71
72 ********************************** 72 **********************************
73 * Power Line Frequency Definitions 73 * Power Line Frequency Definitions
74 * 74 *
75 Hz50 equ 1 Assemble clock for 50 hz power 75 Hz50 EQU 1 Assemble clock for 50 hz power
76 Hz60 equ 2 Assemble clock for 60 hz power 76 Hz60 EQU 2 Assemble clock for 60 hz power
77 PwrLnFrq set Hz60 Set to Appropriate freq 77 PwrLnFrq SET Hz60 Set to Appropriate freq
78 78
79 79
80 ********************************** 80 **********************************
81 * Ticks per second 81 * Ticks per second
82 * 82 *
83 IFEQ PwrLnFrq-Hz50 83 IFEQ PwrLnFrq-Hz50
84 TkPerSec set 50 84 TkPerSec SET 50
85 ELSE 85 ELSE
86 TkPerSec set 60 86 TkPerSec SET 60
87 ENDC 87 ENDC
88 88
89 89
90 ****************** 90 ******************
91 * ACIA type set up 91 * ACIA type set up
92 * 92 *
93 org 1 93 ORG 1
94 ACIA6850 rmb 1 MC6850 acia. 94 ACIA6850 RMB 1 MC6850 acia.
95 ACIA6551 rmb 1 SY6551 acia. 95 ACIA6551 RMB 1 SY6551 acia.
96 ACIA2661 rmb 1 SC2661 acia. 96 ACIA2661 RMB 1 SC2661 acia.
97 ACIATYPE set ACIA6551 97 ACIATYPE SET ACIA6551
98 98
99 99
100 **************************************** 100 ****************************************
101 * Special character Bit position equates 101 * Special character Bit position equates
102 * 102 *
103 SHIFTBIT equ %00000001 103 SHIFTBIT EQU %00000001
104 CNTRLBIT equ %00000010 104 CNTRLBIT EQU %00000010
105 ALTERBIT equ %00000100 105 ALTERBIT EQU %00000100
106 UPBIT equ %00001000 106 UPBIT EQU %00001000
107 DOWNBIT equ %00010000 107 DOWNBIT EQU %00010000
108 LEFTBIT equ %00100000 108 LEFTBIT EQU %00100000
109 RIGHTBIT equ %01000000 109 RIGHTBIT EQU %01000000
110 SPACEBIT equ %10000000 110 SPACEBIT EQU %10000000
111 111
112 112
113 ****************** 113 ******************
114 * Device addresses for miscellaneous hardware 114 * Device addresses for miscellaneous hardware
115 * 115 *
116 A.AciaP set $FF68 Aciapak Address 116 A.AciaP SET $FF68 Aciapak Address
117 A.ModP set $FF6C ModPak Address 117 A.ModP SET $FF6C ModPak Address
118 DPort set $FF40 Disk controller base address 118 DPort SET $FF40 Disk controller base address
119 MPI.Slct set $FF7F Multi-Pak slot select 119 MPI.Slct SET $FF7F Multi-Pak slot select
120 MPI.Slot set $03 Multi-Pak default slot 120 MPI.Slot SET $03 Multi-Pak default slot
121 PIA0Base equ $FF00 121 PIA0Base EQU $FF00
122 PIA1Base equ $FF20 122 PIA1Base EQU $FF20
123 123
124 124
125 ****************** 125 ******************
126 * VDG Devices 126 * VDG Devices
127 * 127 *
128 A.TermV set $FFC0 VDG Term 128 A.TermV SET $FFC0 VDG Term
129 A.V1 set $FFC1 Possible additional VDG Devices 129 A.V1 SET $FFC1 Possible additional VDG Devices
130 A.V2 set $FFC2 130 A.V2 SET $FFC2
131 A.V3 set $FFC3 131 A.V3 SET $FFC3
132 A.V4 set $FFC4 132 A.V4 SET $FFC4
133 A.V5 set $FFC5 133 A.V5 SET $FFC5
134 A.V6 set $FFC6 134 A.V6 SET $FFC6
135 A.V7 set $FFC7 135 A.V7 SET $FFC7
136 136
137 137
138 IFEQ Level-1 138 IFEQ Level-1
139 139
140 ************************************************* 140 *************************************************
141 * 141 *
142 * NitrOS-9 Level 1 Section 142 * NitrOS-9 Level 1 Section
143 * 143 *
144 ************************************************* 144 *************************************************
145 145
146 HW.Page set $FF Device descriptor hardware page 146 HW.Page SET $FF Device descriptor hardware page
147 147
148 ELSE 148 ELSE
149 149
150 ************************************************* 150 *************************************************
151 * 151 *
152 * NitrOS-9 Level 2 Section 152 * NitrOS-9 Level 2 Section
153 * 153 *
154 ************************************************* 154 *************************************************
155 155
156 **************************************** 156 ****************************************
157 * Dynamic Address Translator Definitions 157 * Dynamic Address Translator Definitions
158 * 158 *
159 DAT.BlCt equ 8 D.A.T. blocks/address space 159 DAT.BlCt EQU 8 D.A.T. blocks/address space
160 DAT.BlSz equ (256/DAT.BlCt)*256 D.A.T. block size 160 DAT.BlSz EQU (256/DAT.BlCt)*256 D.A.T. block size
161 DAT.ImSz equ DAT.BlCt*2 D.A.T. Image size 161 DAT.ImSz EQU DAT.BlCt*2 D.A.T. Image size
162 DAT.Addr equ -(DAT.BlSz/256) D.A.T. MSB Address bits 162 DAT.Addr EQU -(DAT.BlSz/256) D.A.T. MSB Address bits
163 DAT.Task equ $FF91 Task Register address 163 DAT.Task EQU $FF91 Task Register address
164 DAT.TkCt equ 32 Number of DAT Tasks 164 DAT.TkCt EQU 32 Number of DAT Tasks
165 DAT.Regs equ $FFA0 DAT Block Registers base address 165 DAT.Regs EQU $FFA0 DAT Block Registers base address
166 DAT.Free equ $333E Free Block Number 166 DAT.Free EQU $333E Free Block Number
167 DAT.BlMx equ $3F Maximum Block number 167 DAT.BlMx EQU $3F Maximum Block number
168 DAT.BMSz equ $40 Memory Block Map size 168 DAT.BMSz EQU $40 Memory Block Map size
169 DAT.WrPr equ 0 no write protect 169 DAT.WrPr EQU 0 no write protect
170 DAT.WrEn equ 0 no write enable 170 DAT.WrEn EQU 0 no write enable
171 SysTask equ 0 Coco System Task number 171 SysTask EQU 0 Coco System Task number
172 IOBlock equ $3F 172 IOBlock EQU $3F
173 ROMBlock equ $3F 173 ROMBlock EQU $3F
174 IOAddr equ $7F 174 IOAddr EQU $7F
175 ROMCount equ 1 number of blocks of ROM (High RAM Block) 175 ROMCount EQU 1 number of blocks of ROM (High RAM Block)
176 RAMCount equ 1 initial blocks of RAM 176 RAMCount EQU 1 initial blocks of RAM
177 MoveBlks equ DAT.BlCt-ROMCount-2 Block numbers used for copies 177 MoveBlks EQU DAT.BlCt-ROMCount-2 Block numbers used for copies
178 BlockTyp equ 1 chk only first bytes of RAM block 178 BlockTyp EQU 1 chk only first bytes of RAM block
179 ByteType equ 2 chk entire block of RAM 179 ByteType EQU 2 chk entire block of RAM
180 Limited equ 1 chk only upper memory for ROM modules 180 Limited EQU 1 chk only upper memory for ROM modules
181 UnLimitd equ 2 chk all NotRAM for modules 181 UnLimitd EQU 2 chk all NotRAM for modules
182 * NOTE: this check assumes any NotRAM with a module will 182 * NOTE: this check assumes any NotRAM with a module will
183 * always start with $87CD in first two bytes of block 183 * always start with $87CD in first two bytes of block
184 RAMCheck equ BlockTyp chk only beg bytes of block 184 RAMCheck EQU BlockTyp chk only beg bytes of block
185 ROMCheck equ Limited chk only upper few blocks for ROM 185 ROMCheck EQU Limited chk only upper few blocks for ROM
186 LastRAM equ IOBlock maximum RAM block number 186 LastRAM EQU IOBlock maximum RAM block number
187 187
188 *************************** 188 ***************************
189 * Color Computer 3 Specific 189 * Color Computer 3 Specific
190 * 190 *
191 MappedIO equ true (Actually False but it works better this way) 191 MappedIO EQU true (Actually False but it works better this way)
192 192
193 ******************** 193 ********************
194 * Hardware addresses 194 * Hardware addresses
195 * 195 *
196 GIMERegs equ $FF00 Base address of GIME registers 196 GIMERegs EQU $FF00 Base address of GIME registers
197 IrqEnR equ $FF92 GIME IRQ enable/status register 197 IrqEnR EQU $FF92 GIME IRQ enable/status register
198 BordReg equ $FF9A Border color register 198 BordReg EQU $FF9A Border color register
199 PalAdr equ $FFB0 Palette registers 199 PalAdr EQU $FFB0 Palette registers
200 200
201 HW.Page set $07 Device descriptor hardware page 201 HW.Page SET $07 Device descriptor hardware page
202 202
203 ENDC 203 ENDC
204 ENDC 204 ENDC
205 205