Mercurial > hg > Members > kono > nitros9-code
diff level1/modules/dwread.asm @ 2741:d1976224b314
Found duplicated code and IFNE H6309-1 statements in dwwrite.asm. Verified it was duplicated code. Must have been accidently copied at some point. Removed second copy of this IFNE H6309-1.
Changed H6309-1 to H6309 and moved the real H6309 code into this routine and moved the standard 6809 57600bps code to the last "else" section. This was done to dwread.asm, dwwrite.asm, dw4write.asm, and dw4read.asm.
Test compiled and everything still seems to compile as it should.
| author | drencor-xeen |
|---|---|
| date | Sun, 06 Jan 2013 11:12:22 -0600 |
| parents | 963688cd0596 |
| children | 8b2df903334c |
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--- a/level1/modules/dwread.asm Sat Jan 05 22:56:05 2013 -0600 +++ b/level1/modules/dwread.asm Sun Jan 06 11:12:22 2013 -0600 @@ -21,7 +21,7 @@ IFNE BECKER * NOTE: There is no timeout currently on here... DWRead pshs cc,d,x,u - leau ,x + leau ,x ldx #$0000 orcc #IntMasks loop@ ldb $FF41 @@ -106,7 +106,70 @@ ELSE - IFNE H6309-1 + IFNE H6309 +******************************************************* +* 57600 (115200) bps using 6309 native mode +******************************************************* + +DWRead clrb ; clear Carry (no framing error) + decb ; clear Z flag, B = $FF + pshs u,x,dp,cc ; preserve registers + orcc #$50 ; mask interrupts +* ldmd #1 ; requires 6309 native mode + tfr b,dp ; set direct page to $FFxx + setdp $ff + leay -1,y ; adjust request count + leau ,x ; U = storage ptr + tfr 0,x ; initialize checksum + lda #$01 ; A = serial in mask + bra rx0030 ; go wait for start bit + +* Read a byte +rxByte sexw ; 4 cycle delay + ldw #$006a ; shift counter and timing flags + clra ; clear carry so next will branch +rx0010 bcc rx0020 ; branch if even bit number (15 cycles) + nop ; extra (16th) cycle +rx0020 lda <BBIN ; read bit + lsra ; move bit into carry + rorb ; rotate bit into byte accumulator + lda #0 ; prep A for 8th data bit + lsrw ; bump shift count, timing bit to carry + bne rx0010 ; loop until 7th data bit has been read + incw ; W = 1 for subtraction from Y + inca ; A = 1 for reading bit 7 + anda <BBIN ; read bit 7 + lsra ; move bit 7 into carry, A = 0 + rorb ; byte is now complete + stb ,u+ ; store received byte to memory + abx ; update checksum + subr w,y ; decrement request count + inca ; A = 1 for reading stop bit + anda <BBIN ; read stop bit + bls rxExit ; exit if completed or framing error + +* Wait for a start bit or timeout +rx0030 clrw ; initialize timeout counter +rx0040 bita <BBIN ; check for start bit + beq rxByte ; branch if start bit detected + addw #1 ; bump timeout counter + bita <BBIN + beq rxByte + bcc rx0040 ; loop until timeout rolls over + lda #$03 ; setup to return TIMEOUT status + +* Clean up, set status and return +rxExit beq rx0050 ; branch if framing error + eora #$02 ; toggle SUCCESS flag +rx0050 inca ; A = status to be returned in C and Z + ora ,s ; place status information into the.. + sta ,s ; ..C and Z bits of the preserved CC + leay ,x ; return checksum in Y + puls cc,dp,x,u,pc ; restore registers and return + setdp $00 + + + ELSE ******************************************************* * 57600 (115200) bps using 6809 code and timimg ******************************************************* @@ -197,69 +260,6 @@ puls cc,dp,x,u,pc ; restore registers and return setdp $00 - - ELSE -******************************************************* -* 57600 (115200) bps using 6309 native mode -******************************************************* - -DWRead clrb ; clear Carry (no framing error) - decb ; clear Z flag, B = $FF - pshs u,x,dp,cc ; preserve registers - orcc #$50 ; mask interrupts -* ldmd #1 ; requires 6309 native mode - tfr b,dp ; set direct page to $FFxx - setdp $ff - leay -1,y ; adjust request count - leau ,x ; U = storage ptr - tfr 0,x ; initialize checksum - lda #$01 ; A = serial in mask - bra rx0030 ; go wait for start bit - -* Read a byte -rxByte sexw ; 4 cycle delay - ldw #$006a ; shift counter and timing flags - clra ; clear carry so next will branch -rx0010 bcc rx0020 ; branch if even bit number (15 cycles) - nop ; extra (16th) cycle -rx0020 lda <BBIN ; read bit - lsra ; move bit into carry - rorb ; rotate bit into byte accumulator - lda #0 ; prep A for 8th data bit - lsrw ; bump shift count, timing bit to carry - bne rx0010 ; loop until 7th data bit has been read - incw ; W = 1 for subtraction from Y - inca ; A = 1 for reading bit 7 - anda <BBIN ; read bit 7 - lsra ; move bit 7 into carry, A = 0 - rorb ; byte is now complete - stb ,u+ ; store received byte to memory - abx ; update checksum - subr w,y ; decrement request count - inca ; A = 1 for reading stop bit - anda <BBIN ; read stop bit - bls rxExit ; exit if completed or framing error - -* Wait for a start bit or timeout -rx0030 clrw ; initialize timeout counter -rx0040 bita <BBIN ; check for start bit - beq rxByte ; branch if start bit detected - addw #1 ; bump timeout counter - bita <BBIN - beq rxByte - bcc rx0040 ; loop until timeout rolls over - lda #$03 ; setup to return TIMEOUT status - -* Clean up, set status and return -rxExit beq rx0050 ; branch if framing error - eora #$02 ; toggle SUCCESS flag -rx0050 inca ; A = status to be returned in C and Z - ora ,s ; place status information into the.. - sta ,s ; ..C and Z bits of the preserved CC - leay ,x ; return checksum in Y - puls cc,dp,x,u,pc ; restore registers and return - setdp $00 - ENDC ENDC ENDC