# HG changeset patch # User Boisy Pitre # Date 1494969926 -7200 # Node ID b1efa6891f4e06254c947396a8d61928958418f0 # Parent 504992b73b2be62c04f526f54dc53fbdb731ea11 Add sc6850 SCF driver for Motorola MC6850 ACIA (UART) Add PARMASK definition to scf.d diff -r 504992b73b2b -r b1efa6891f4e defs/scf.d --- a/defs/scf.d Tue May 16 18:57:25 2017 +0200 +++ b/defs/scf.d Tue May 16 23:25:26 2017 +0200 @@ -219,6 +219,7 @@ PAREVEN EQU %01100000 PARMARK EQU %10100000 PARSPACE EQU %11100000 +PARMASK EQU %11100000 * PD.BAU definitions * diff -r 504992b73b2b -r b1efa6891f4e level1/modules/sc6850.asm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/modules/sc6850.asm Tue May 16 23:25:26 2017 +0200 @@ -0,0 +1,947 @@ +******************************************************************** +* sc6850 - Motorola 6850 UART Driver +* +* $Id$ +* +* Data sheet for 6850 is here: +* http://www.classiccmp.org/dunfield/r/6850.pdf +* +* Edt/Rev YYYY/MM/DD Modified by +* Comment +* ------------------------------------------------------------------ +* 1 2017/05/08 Boisy G. Pitre +* Created for Corsham 6809 +* + + nam sc6850 + ttl Motorola 6850 UART Driver + + ifp1 + use defsfile + endc + +* miscellaneous definitions +DCDStBit equ %00100000 DCD status bit for SS.CDSta call +DSRStBit equ %01000000 DSR status bit for SS.CDSta call +SlpBreak set TkPerSec/2+1 line Break duration +SlpHngUp set TkPerSec/2+1 hang up (drop DTR) duration + +* +* 6850 Register Definitions +* + org 0 +StatReg rmb 1 +CtlReg equ StatReg +DataReg rmb 1 + +* 6850 Status Register Bit Definitions +Stat.IRQ equ %10000000 IRQ occurred +Stat.Par equ %01000000 Rx data Parity error +Stat.Ovr equ %00100000 Rx data Overrun error +Stat.Frm equ %00010000 Rx data Framing error +Stat.CTS equ %00001000 Rx data Framing error +Stat.DCD equ %00000100 Rx data Framing error +Stat.TxE equ %00000010 Tx data register Empty +Stat.RxF equ %00000001 Rx data register Full +Stat.Err equ Stat.Ovr!Stat.Frm!Stat.Par Status error bits +Stat.Flp equ $00 all Status bits active when set +Stat.Msk equ Stat.IRQ!Stat.RxF active IRQs + +* 6850 Control Register Bit Definitions +Ctl.RxIEn equ %10000000 Rx interrupt enable +Ctl.tc1 equ %01000000 Transmitter control 1 +Ctl.tc0 equ %00100000 Transmitter control 0 +Ctl.ws2 equ %00010000 +Ctl.ws1 equ %00001000 +Ctl.ws0 equ %00000100 +Ctl.cds0 equ %00000001 +Ctl.cds1 equ %00000010 +Ctl.BauMsk equ Ctl.cds0!Ctl.cds1 +Ctl.WrdMsk equ Ctl.ws2!Ctl.ws1|Ctl.ws0 +Ctl.TCMsk equ Ctl.tc1!Ctl.tc0 +Ctl.Reset equ Ctl.cds1|Ctl.cds0 + +* 6850 Bit/Parity/Stop definitions +Ctl.8O1 equ Ctl.ws2!Ctl.ws1|Ctl.ws0 +Ctl.8E1 equ Ctl.ws2!Ctl.ws1 +Ctl.8N1 equ Ctl.ws2!Ctl.ws0 +Ctl.8N2 equ Ctl.ws2 +Ctl.7O1 equ Ctl.ws1|Ctl.ws0 +Ctl.7E1 equ Ctl.ws1 +Ctl.7O2 equ Ctl.ws0 +Ctl.7E2 equ 0 + +* Command bit definitions +Cmd.TIRB equ %00001100 see Tx IRQ/RTS/Break table below +Cmd.DTR equ %00000001 DTR output (set=enabled) + +* Tx IRQ/RTS/Break table +TIRB.Off equ %00000000 RTS & Tx IRQs disabled +TIRB.On equ %00000100 RTS & Tx IRQs enabled +TIRB.RTS equ %00001000 RTS enabled, Tx IRQs disabled +TIRB.Brk equ %00001100 RTS enabled, Tx IRQs disabled, Tx line Break + +* V.ERR bit definitions +DCDLstEr equ %00100000 DCD lost error +OvrFloEr equ %00000100 Rx data overrun or Rx buffer overflow error +FrmingEr equ %00000010 Rx data framing error +ParityEr equ %00000001 Rx data parity error + +* FloCtlRx bit definitions +FCRxSend equ %10000000 send flow control character +FCRxSent equ %00010000 Rx disabled due to XOFF sent +FCRxDTR equ %00000010 Rx disabled due to DTR +FCRxRTS equ %00000001 Rx disabled due to RTS + +* FloCtlTx bit definitions +FCTxXOff equ %10000000 due to XOFF received +FCTxBrk equ %00000010 due to currently transmitting Break + +* Wrk.Type bit definitions +Parity equ %11100000 parity bits +MdmKill equ %00010000 modem kill option +RxSwFlow equ %00001000 Rx data software (XON/XOFF) flow control +TxSwFlow equ %00000100 Tx data software (XON/XOFF) flow control +RTSFlow equ %00000010 CTS/RTS hardware flow control +DSRFlow equ %00000001 DSR/DTR hardware flow control + +* Wrk.XTyp bit definitions +SwpDCDSR equ %10000000 swap DCD+DSR bits (valid for 6551 only) +ForceDTR equ %01000000 don't drop DTR in term routine +RxBufPag equ %00001111 input buffer page count + +* static data area definitions + org V.SCF allow for SCF manager data area +Cpy.Stat rmb 1 Status register copy +CpyDCDSR rmb 1 DSR+DCD status copy +Mask.DCD rmb 1 DCD status bit mask (MUST immediately precede Mask.DSR) +Mask.DSR rmb 1 DSR status bit mask (MUST immediately follow Mask.DCD) +CDSigPID rmb 1 process ID for CD signal +CDSigSig rmb 1 CD signal code +FloCtlRx rmb 1 Rx flow control flags +FloCtlTx rmb 1 Tx flow control flags +RxBufEnd rmb 2 end of Rx buffer +RxBufGet rmb 2 Rx buffer output pointer +RxBufMax rmb 2 Send XOFF (if enabled) at this point +RxBufMin rmb 2 Send XON (if XOFF sent) at this point +RxBufPtr rmb 2 pointer to Rx buffer +RxBufPut rmb 2 Rx buffer input pointer +RxBufSiz rmb 2 Rx buffer size +RxDatLen rmb 2 current length of data in Rx buffer +SigSent rmb 1 keyboard abort/interrupt signal already sent +SSigPID rmb 1 SS.SSig process ID +SSigSig rmb 1 SS.SSig signal code +WritFlag rmb 1 initial write attempt flag +Wrk.Type rmb 1 type work byte (MUST immediately precede Wrk.Baud) +Wrk.Baud rmb 1 baud work byte (MUST immediately follow Wrk.Type) +Wrk.XTyp rmb 1 extended type work byte + +regWbuf rmb 2 substitute for regW +RxBufDSz equ 256-. default Rx buffer gets remainder of page... +RxBuff rmb RxBufDSz default Rx buffer +MemSize equ . + +rev set 0 +edition set 1 + + mod ModSize,ModName,Drivr+Objct,ReEnt+rev,ModEntry,MemSize + + fcb UPDAT. access mode(s) + +ModName fcs "sc6850" + fcb edition + + +* These 3 bytes control how the IRQ ISR processes interrupts from this +* device +IRQPckt equ * +Pkt.Flip fcb Stat.Flp flip byte +Pkt.Mask fcb Stat.Msk mask byte + fcb $0A priority + +* NOTE: SCFMan has already cleared all device memory except for V.PAGE and +* V.PORT. Zero-default variables are: CDSigPID, CDSigSig, Wrk.XTyp. +* Entry: +* Y = address of the device descriptor +* U = address of the device memory area +* +* Exit: +* CC = carry set on error +* B = error code +Init + pshs cc,dp save IRQ/Carry status, system DP + IFNE H6309 + tfr u,w + tfr e,dp + tfr y,w save descriptor pointer + ELSE + tfr u,d get device memory area + tfr a,dp and make it the direct page + pshs y save descriptor pointer + ENDC + +* Register the ISR +* D address of the device status register +* X address of the "packet" containing the flip/mask/priority +* Y address of the device IRQ service routine +* U address of the device IRQ service routine memory + ldd D.Proc + lda P$ID,x + sta D.Proc process descriptor address + sta D.Proc process descriptor address + ldb P$Signal,x pending signal for this process? + beq ChkState no, go check process state... + cmpb #S$Intrpt do we honor signal? + lbls ErrExit yes, go do it... +ChkState equ * + IFNE H6309 + tim #Condem,P$State,x + ELSE + ldb P$State,x + bitb #Condem + ENDC + bne PrAbtErr yes, go do it... + ldb NOT extended type +initsize equ * + + IFDEF TNum from makefile + IFEQ TNum +name fcs /T0/ + ENDIF + IFEQ TNum-1 +name fcs /T1/ + ENDIF + ELSE +name fcs /Term/ + ENDIF match IFDEF TNum + +mgrnam fcs /SCF/ +drvnam fcs /sc6850/ + + emod +eom equ * + end