Mercurial > hg > Members > kono > nitros9-code
changeset 3182:185c31229f22
Add level1 corsham port for the Corsham 6809 System
Apart from the new level1/corsham tree, some conditional code was
added to common code. No change to other ports.
http://www.corshamtech.com/
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/defs/corsham.d Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,204 @@ + ifne CORSHAM.D-1 +CORSHAM.D set 1 + +******************************************************************** +* corsham.d - NitrOS-9 System Definitions for the Corsham 6809 +* +* This is a high level view of the Corsham 6809 memory map as setup by +* NitrOS-9. +* +* $0000----> ================================== +* | | +* | NitrOS-9 Globals/Stack | +* | | +* $0500---->|==================================| +* | | +* . . . . . . . . . . . . . . . . . +* | | +* | RAM available for allocation | +* | by NitrOS-9 and Apps | +* | | +* . . . . . . . . . . . . . . . . . +* | | +* $E000---->|==================================| +* | | +* $E000-$EFFF | Memory Mapped I/O Region | +* | | +* $F000---->|==================================| +* | | +* $F000-$FFFF | ROM | +* | | +* |==================================| +* +* $Id$ +* +* Edt/Rev YYYY/MM/DD Modified by +* Comment +* ------------------------------------------------------------------ +* 2017/04/29 Boisy G. Pitre +* Started + + nam corsham.d + ttl NitrOS-9 System Definitions for the Corsham 6809 + +********************************** +* Ticks per second +* + IFNDEF TkPerSec +TkPerSec SET 50 + ENDC + + +************************************************* +* +* NitrOS-9 Level 1 Section +* +************************************************* + +HW.Page set $E0 Device descriptor hardware page + + +******************************************************************** +* NitrOS-9 Memory Definitions for the Corsham 6809 +* + +******************************************************************** +* Corsham 6809 Hardware Definitions +* + +DATREGS equ $FFF0 DAT RAM CHIP + + +S.CharOut EQU $FFE9 +S.StringOut EQU $FFEB + +PSETWR equ $F006 ; PIA Set Write Mode +PSETRE equ $F009 ; PIA Set Read Mode +PREAD equ $F00F ; PIA Read Byte +PWRITE equ $F00C ; PIA Write Byte +CSETIMR equ $1E ; Set Timer Command to Arduino +RACK equ $82 ; Command Ack from Arduino + +CONSLOT equ 1 console slot +SDSLOT equ 6 SD card slot +SLOTSIZ equ 16 +IOBASE equ $E000 + +;---------------------------------------------------- +; +; Which slot the parallel board is in. This needs to +; be set for the system in use. As long as the user +; programs only call functions in here, no other +; file/application should know which slot the board +; is in. + +PIA0Base equ SDSLOT*SLOTSIZ+IOBASE +UARTBase equ CONSLOT*SLOTSIZ+IOBASE + +PIAREGA equ 0 ;data reg A +PIADDRA equ 0 ;data dir reg A +PIACTLA equ 1 ;control reg A +PIAREGB equ 2 ;data reg B +PIADDRB equ 2 ;data dir reg B +PIACTLB equ 3 ;control reg B + +;---------------------------------------------------- +; Bits in the B register +; +DIRECTION equ %00000001 +PSTROBE equ %00000010 +ACK equ %00000100 +; + + org $DFC0 +C.STACK RMB 2 TOP OF INTERNAL STACK / USER VECTOR +C.SWI3 RMB 2 SOFTWARE INTERRUPT VECTOR #3 +C.SWI2 RMB 2 SOFTWARE INTERRUPT VECTOR #2 +C.FIRQ RMB 2 FAST INTERRUPT VECTOR +C.IRQ RMB 2 INTERRUPT VECTOR +C.SWI RMB 2 SOFTWARE INTERRUPT VECTOR +SVCVO RMB 2 SUPERVISOR CALL VECTOR ORGIN +SVCVL RMB 2 SUPERVISOR CALL VECTOR LIMIT +LRARAM RMB 16 LRA ADDRESSES + +Bt.Start EQU $F000 Start address of the boot ROM in memory +Bt.Size EQU $1000 + +;***************************************************** +; Parallel port protocol +; +; This is the header file for making applications +; compliant with The Remote Disk Protocol Guide which +; is on the Corsham Technologies web page somewhere: +; +; www.corshamtech.com +; +; This was updated 06/13/2015 to be compliant with the +; official specification, so the opcode values changed. +; +;===================================================== +; Commands from host to Arduino +; +PC_GET_VERSION equ $01 +PC_PING equ $05 ;ping Arduino +PC_LED_CONTROL equ $06 ;LED control +PC_GET_CLOCK equ $07 ;Get RTC +PC_SET_CLOCK equ $08 ;Set RTC +PC_GET_DIR equ $10 ;Get directory +PC_GET_MOUNTED equ $11 ;Get mounted drive list +PC_MOUNT equ $12 ;Mount drive +PC_UNMOUNT equ $13 ;Unmount drive +PC_GET_STATUS equ $14 ;Get status for one drive +PC_DONE equ $15 ;Stop data +PC_ABORT equ PC_DONE +PC_READ_FILE equ $16 ;Read regular file (non-DSK) +PC_READ_BYTES equ $17 ;Read sequential bytes +PC_RD_SECTOR equ $18 ;Read FLEX sector +PC_WR_SECTOR equ $19 ;Write FLEX sector +PC_GET_MAX equ $1a ;Get maximum drives +PC_WRITE_FILE equ $1b ;Open file for writing +PC_WRITE_BYTES equ $1c ;Data to be written +PC_SAVE_CONFIG equ $1d ;Save current config data to file +PC_SET_TIMER equ $1e ;Turn on/off RTC timer +PC_READ_LONG equ $1f ;read sector using long sector num +PC_WRITE_LONG equ $20 ;write sector using long sec number +; +;===================================================== +; Responses from Arduino to host +; +PR_VERSION_INFO equ $81 ;Contains version information +PR_ACK equ $82 ;ACK (no additional information) +PR_NAK equ $83 ;NAK - one status byte follows +PR_PONG equ $85 ;Reply to a ping +PR_CLOCK_DATA equ $87 ;Clock data +PR_DIR_ENTRY equ $90 ;Directory entry +PR_DIR_END equ $91 ;End of directory entries +PR_FILE_DATA equ $92 ;File data +PR_STATUS equ $93 ;Drive status +PR_SECTOR_DATA equ $94 ;Sector data +PR_MOUNT_INFO equ $95 ;Mount entry +PR_MAX_DRIVES equ $96 ;Maximum number of drives +; +;===================================================== +; Error codes for NAK events +; +ERR_NONE equ 00 +ERR_NOT_MOUNTED equ 10 +ERR_MOUNTED equ 11 +ERR_NOT_FOUND equ 12 +ERR_READ_ONLY equ 13 +ERR_BAD_DRIVE equ 14 +ERR_BAD_TRACK equ 15 +ERR_BAD_SECTOR equ 16 +ERR_READ_ERROR equ 17 + +;===================================================== +; PIO subroutine module offsets +; + org 0 +PIO$Init rmb 3 +PIO$Read rmb 3 +PIO$Write rmb 3 +PIO$Term rmb 3 + + endc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/bootfiles/makefile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,29 @@ +include ../port.mak + +# Module directory +MD = ../modules +# Commands directory +CMDSDIR = ../cmds + +DEPENDS = ./makefile + +BOOTFILE = $(MD)/ioman $(MD)/sysgo \ + $(MD)/clock $(MD)/clock2_cshsd \ + $(MD)/scf.mn \ + $(MD)/sc6850.dr $(MD)/term_sc6850.dt \ + $(MD)/rbf.mn \ + $(MD)/rbcshsd.dr $(MD)/ddh0.dd $(MD)/h1.dd $(MD)/h2.dd $(MD)/h3.dd \ + $(MD)/pio.sb $(CMDSDIR)/shell_21 + +BOOTFILES = bootfile + +ALLOBJS = $(BOOTFILES) + +all: $(ALLOBJS) + +bootfile: $(BOOTFILE) $(DEPENDS) + $(MERGE) $(BOOTFILE)>$@ + +clean: + $(RM) $(ALLOBJS) +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/bootrom/makefile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,26 @@ +include ../port.mak + +# Module directory +MD = ../modules +# Commands directory +CMDSDIR = ../cmds + +DEPENDS = ./makefile + +BOOTROM = $(MD)/kernel/krn $(MD)/kernel/krnp2 $(MD)/init $(MD)/boot_cshsd +ALLOBJS = $(BOOTROM) + +all: bootrom + +bootrom: $(BOOTROM) + $(MERGE) $(BOOTROM) > bootrom_p1 + ls -l bootrom_p1 + $(PADROM) 3840 bootrom_p1 + $(MERGE) bootrom_p1 $(MD)/rel > $@ + ls -l $@ + $(PADROM) 8192 -b $@ + $(RM) bootrom_p1 + +clean: + $(RM) bootrom bootrom_p1 +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/cmds/defsfile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,1 @@ + use ../defsfile
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/cmds/makefile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,54 @@ +include ../port.mak + +vpath %.as $(LEVEL1)/cmds +vpath %.asm $(LEVEL1)/cmds:$(3RDPARTY)/packages/basic09 + +DEPENDS = ./makefile + +AFLAGS += --includedir=$(3RDPARTY)/packages/basic09 +LFLAGS += -L $(NITROS9DIR)/lib -lnet -latari -lalib + +BASIC09FILES = basic09.asm runb.asm gfx.asm inkey.asm syscall.asm +CMDS = asm attr backup binex build calldbg cmp copy cputype \ + date dcheck debug ded deiniz del deldir devs dir dirsort disasm \ + display dmode dsave dump echo edit error exbin format \ + free help ident iniz irqs link list load login makdir \ + megaread mdir merge mfree os9gen padrom park printerr procs prompt pwd pxd \ + rename save setime shellplus shell_21 sleep \ + tee tmode touch tsmon tuneport unlink verify xmode\ + basic09 runb gfx inkey syscall + +SUBS = gfx inkey syscall +ALLOBJS = $(CMDS) $(SUBS) + +all: $(ALLOBJS) + +pwd: pd.asm + $(AS) $(AFLAGS) $< $(ASOUT)$@ -DPWD=1 + +xmode: xmode.asm + $(AS) $(AFLAGS) $< $(ASOUT)$@ -DXMODE=1 + +tmode: xmode.asm + $(AS) $(AFLAGS) $< $(ASOUT)$@ -DTMODE=1 + +pxd: pd.asm + $(AS) $(AFLAGS) $< $(ASOUT)$@ -DPXD=1 + +clean: + $(RM) $(ALLOBJS) + +identify: + $(IDENT_SHORT) $(ALLOBJS) + +showobjs: + @$(ECHO) $(CMDS) + +showobjs_dw: + @$(ECHO) $(CMDS) + +showobjs_demo: + @$(ECHO) $(CMDS_DEMO) + +showallobjs: + @$(ECHO) $(ALLOBJS)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/defs/defsfile.asm Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,8 @@ +Level equ 1 + + ifp1 + use /dd/defs/os9.d + use /dd/defs/rbf.d + use /dd/defs/scf.d + use /dd/defs/atari.d + endc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/defs/makefile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,31 @@ +include ../port.mak + +DEPENDS = ./makefile + +DEFOPTS = --preprocess -DLevel=1 +DEFSDIR = ../../../defs +DEFS = defsfile os9.d rbf.d scf.d corsham.d +ALLOBJS = $(DEFS) + +all: $(ALLOBJS) + +defsfile: defsfile.asm + $(AS) $(DEFOPTS) $< > $@ + +os9.d: $(DEFSDIR)/os9.d + $(AS) $(DEFOPTS) -DOS9.D=0 $< > $@ + +rbf.d: $(DEFSDIR)/rbf.d + $(AS) $(DEFOPTS) -DRBF.D=0 $< > $@ + +scf.d: $(DEFSDIR)/scf.d + $(AS) $(DEFOPTS) -DSCF.D=0 $< > $@ + +corsham.d: $(DEFSDIR)/corsham.d + $(AS) $(DEFOPTS) -DATARI.D=0 $< > $@ + +clean: + $(RM) $(DEFS) + +showobjs: + @$(ECHO) $(ALLOBJS)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/defsfile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,6 @@ +Level equ 1 + + use os9.d + use scf.d + use rbf.d + use corsham.d
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/makefile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,69 @@ +include port.mak + +# Level 1 - Specify which shell should be used +#WHICHSHELL = shellplus +WHICHSHELL = shell_21 + +DISTRO = $(CPU)L$(LEVEL) +DISTRONAME = nos9$(CPU)l$(LEVEL) +DISTROVER = $(DISTRONAME)$(NITROS9VER)$(PORT) +BOOTFILE = bootfiles/bootfile +DIRS = cmds modules defs sys bootfiles + + +CMDS = $(shell $(CD) cmds; make --no-print-directory showobjs) +CMDS_DEMO = $(shell $(CD) cmds; make --no-print-directory showobjs_demo) +SYS = $(shell $(CD) sys; make --no-print-directory showobjs) +DEFS = $(shell $(CD) defs; make --no-print-directory showobjs) +STARTUP = startup + +DSK = $(DISTROVER).dsk + +DSKS = $(DSK) + +# Make all components +all: + @$(ECHO) "************************************************************" + @$(ECHO) "*" + @$(ECHO) "* NitrOS-9/$(CPU) Level $(LEVEL) $(MACHINE) ($(PORT))" + @$(ECHO) "*" + @$(ECHO) "************************************************************" + $(foreach dir,$(DIRS),$(MAKE) -C $(dir) &&) : + +# Clean all components +clean: dskclean + $(foreach dir,$(DIRS),$(MAKE) -C $(dir) clean &&) : + +dskclean: + $(RM) $(DSKS) + +dsk: all $(DSKS) + +copyToSDAndEject: $(DSK) + $(CP) $(DSK) /Volumes/CORSHAM/NOS9.DSK + diskutil eject /Volumes/CORSHAM + +dskcopy: $(DSKS) + $(CP) $(DSKS) $(DSKDIR) + +$(DSK): + $(RM) $@ + $(OS9FORMAT_DW) -e -q $@ -n"NitrOS-9/$(CPU) Level 1" + $(OS9GEN) $@ -b=$(BOOTFILE) + $(MAKDIR) $@,CMDS + $(MAKDIR) $@,SYS + $(MAKDIR) $@,DEFS + $(CD) cmds; $(OS9COPY) $(CMDS) ../$@,CMDS + $(OS9ATTR_EXEC) $(foreach file,$(CMDS),$@,CMDS/$(file)) + $(OS9RENAME) $@,CMDS/$(WHICHSHELL) shell + $(CD) sys; $(CPL) $(SYS) ../$@,SYS + $(OS9ATTR_TEXT) $(foreach file,$(SYS),$@,SYS/$(file)) + $(CD) defs; $(CPL) $(DEFS) ../$@,DEFS + $(OS9ATTR_TEXT) $(foreach file,$(DEFS),$@,DEFS/$(file)) + $(CPL) $(STARTUP) $@,startup + $(OS9ATTR_TEXT) $@,startup + +info: + @$(ECHO) "*** NitrOS-9/6809 Level 1 for the Corsham 6809 SS-50 ***" + @$(foreach dsk, $(DSKS), $(ECHO) $(dsk);) +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/modules/boot_cshsd.asm Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,308 @@ +******************************************************************** +* Boot - Corsham SD Boot module +* Provides HWInit, HWTerm, HWRead which are called by code in +* "use"d boot_common.asm +* +* $Id$ +* +* Edt/Rev YYYY/MM/DD Modified by +* Comment +* ------------------------------------------------------------------ +* 2017/05/01 Darren Atkinson +* Created. + + nam Boot + ttl Corsham SD Boot module + + IFP1 + use defsfile + ENDC + + org 0 +* Default Boot is from drive 0 +BootDr set 0 + +* Alternate Boot is from drive 1 + IFEQ DNum-1 +BootDr set 1 + ENDC + +* Common booter-required defines +LSN24BIT equ 1 +FLOPPY equ 0 + +* NOTE: these are U-stack offsets, not DP +seglist rmb 2 pointer to segment list +blockloc rmb 2 pointer to memory requested +blockimg rmb 2 duplicate of the above +bootsize rmb 2 size in bytes +LSN0Ptr rmb 2 In memory LSN0 pointer +size equ . + + +tylg set Systm+Objct +atrv set ReEnt+rev +rev set $00 +edition set 1 + + mod eom,name,tylg,atrv,start,size + +name fcs /Boot/ + fcb edition + + +*-------------------------------------------------------------------------- +* HWInit - Initialize the device +* +* Entry: +* Y = hardware address +* +* Exit: +* Carry Clear = OK, Set = Error +* B = error (Carry Set) +* +HWInit +; +; Set up the data direction register for port B so that +; the DIRECTION and PSTROBE bits are output. +; + ldx #PIA0Base + clr PIACTLB,x ;select DDR ...for port B + ldd #$04*256+DIRECTION|PSTROBE + stb PIADDRB,x + sta PIACTLB,x + lbsr xParSetWrite + +*-------------------------------------------------------------------------- +* HWTerm - Terminate the device +* +* Entry: +* Y = hardware address +* +* Exit: +* Carry Clear = OK, Set = Error +* B = error (Carry Set) +* +HWTerm clrb no error + rts + +*************************************************************************** + use boot_common.asm +*************************************************************************** + +* +* HWRead - Read a 256 byte sector from the device +* +* Entry: +* Y = hardware address +* B = bits 23-16 of LSN +* X = bits 15-0 of LSN +* blockloc,u = where to load the 256 byte sector +* +* Exit: +* Carry Clear = OK, Set = Error +* +HWRead + ldy blockloc,u + +;===================================================== +; This is a low level disk function for a real OS to +; perform a disk sector read using a single long +; sector number. On entry, X points to a disk +; parameter block with the following fields: +; +; B = sector bits 23-16 +; X = sector bits 15-0 +; Y = address to store 256 byte buffer +; +; The drive and sector number are zero based. +; +; Returns with C clear on success. If error, C is set +; and A contains the error code. +; +DiskReadLong lda #PC_READ_LONG + bsr xParWriteByte + clra + bsr xParWriteByte ;drive + lda #2 ;256 byte sectors + bsr xParWriteByte +; +; Now send the four byte sector number. +; + clra + bsr xParWriteByte + tfr b,a + bsr xParWriteByte + tfr x,d + bsr xParWriteByte + tfr b,a + bsr xParWriteByte +;***************************************************** +; This sets up for reading from the Arduino. Sets up +; direction registers, clears the direction bit, etc. +; +xParSetRead ;select DDR + ldx #PIA0Base + clr PIACTLA,x ;...for port A + clr PIADDRA,x + lda #4 ;select data reg + sta PIACTLA,x +; +; Set direction flag to input, clear ACK bit +; + clr PIAREGB,x + + bsr xParReadByte ;response + cmpa #PR_SECTOR_DATA ;data? + bne DiskCerror ;no +; + lda #'. + jsr [S.CharOut] + clrb ;256 bytes of data +DiskReadLp bsr xParReadByte + sta ,y+ + decb + bne DiskReadLp +; +; All done +; +;***************************************************** +; This sets up for writing to the Arduino. Sets up +; direction registers, drives the direction bit, etc. +; +xParSetWrite clra ;select DDR + sta PIACTLA,x ;...for port A + deca ; $FF set bits for output + sta PIADDRA,x + lda #4 ;select data reg + sta PIACTLA,x +; +; Set direction flag to output, clear ACK bit +; + lda #DIRECTION + sta PIAREGB,x + + ldx blockloc,u + + clrb + rts + +; +; Common error handler. Next byte is the error code +; which goes into B, set carry, and exit. +; +DiskCerror bsr xParReadByte + lda #'? + jsr [S.CharOut] + comb + ldb #E$Read + rts + + +;***************************************************** +; This writes a single byte to the Arduino. On entry, +; the byte to write is in A. This assumes ParSetWrite +; was already called. +;; +; Write cycle: +; +; 1. Wait for other side to lower ACK. +; 2. Put data onto the bus. +; 3. Set DIRECTION and PSTROBE to indicate data +; is valid and ready to read. +; 4. Wait for ACK line to go high, indicating the +; other side has read the data. +; 5. Lower PSTROBE. +; 6. Wait for ACK to go low, indicating end of +; transfer. +; +xParWriteByte pshs b,x ;save data + ldx #PIA0Base +Parwl22 ldb PIAREGB,x ;check status + andb #ACK + bne Parwl22 ;wait for ACK to go low +; +; Now put the data onto the bus +; + sta PIAREGA,x +; +; Raise the strobe so the Arduino knows there is +; new data. +; + lda PIAREGB,x + ora #PSTROBE + sta PIAREGB,x +; +; Wait for ACK to go high, indicating the Arduino has +; pulled the data and is ready for more. +; +Parwl33 lda PIAREGB,x + anda #ACK + beq Parwl33 +; +; Now lower the strobe, then wait for the Arduino to +; lower ACK. +; + lda PIAREGB,x + anda #~PSTROBE + sta PIAREGB,x +Parwl44 lda PIAREGB,x + anda #ACK + bne Parwl44 + puls b,x,pc + +;***************************************************** +; This reads a byte from the Arduino and returns it in +; A. Assumes ParSetRead was called before. +; +; This does not have a time-out. +; +; Preserves all other registers. +; +; Read cycle: +; +; 1. Wait for other side to raise ACK, indicating +; data is ready. +; 2. Read data. +; 3. Raise PSTROBE indicating data was read. +; 4. Wait for ACK to go low. +; 5. Lower PSTROBE. +; +xParReadByte pshs a,x + ldx #PIA0Base +parloop@ lda PIAREGB,x + anda #ACK ;is their strobe high? + beq parloop@ ;nope, no data +; +; Data is available, so grab and save it. +; + lda PIAREGA,x + sta ,s +; +; Now raise our strobe (their ACK), then wait for +; them to lower their strobe. +; + lda PIAREGB,x + ora #PSTROBE + sta PIAREGB,x +Parrlp1 lda PIAREGB,x + anda #ACK + bne Parrlp1 ;still active +; +; Lower our ack, then we're done. +; + lda PIAREGB,x + anda #~PSTROBE + sta PIAREGB,x + puls a,x,pc + + + page + +Address fdb $0000 + + emod +eom equ * +EOMSize equ *-Address + + end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/modules/clock2_cshsd.asm Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,148 @@ +******************************************************************** +* Clock2 - Corsham RTC Driver +* +* $Id$ +* +* Edt/Rev YYYY/MM/DD Modified by +* Comment +* ------------------------------------------------------------------ +* 1 2017/05/11 Boisy G. Pitre +* Created. + + nam Clock2 + ttl Corsham RTC Driver + + ifp1 + use defsfile + endc + +tylg set Sbrtn+Objct +atrv set ReEnt+rev +rev set $00 +edition set 1 + + +RTC.Base equ $0000 + + mod eom,name,tylg,atrv,JmpTable,RTC.Base + +name fcs "Clock2" + fcb edition + +subname fcs "pio" + +* Three Entry Points: +* - Init +* - GetTime +* - SetTIme +JmpTable + lbra Init + bra GetTime RTC Get Time + nop + +SetTime + pshs u,y,x,d + IFGT Level-1 + ldu <D.DWSubAddr + ELSE + ldu >D.DWSubAddr + ENDC + lbeq UpdLeave in case we failed to link it, just exit + lda #PC_SET_CLOCK + pshs a + ldy #$0001 + leax ,s + jsr PIO$Write,u + puls a + ldy #$0000 + leas -8,s + leax ,s + lda D.Year,y year + suba #100 + sta 3,x + lda D.Month,y month + sta ,x + lda D.Day,y day + sta 1,x + lda D.Hour,y hour + sta 4,x + lda D.Min,y minute + sta 5,x + lda D.Sec,y second + sta 6,x + lda #1 + sta 2,x + ldy #$0008 + jsr PIO$Write,u +* read ack byte + ldy #1 + jsr PIO$Read,u + leas 8,s + bra UpdLeave + +GetTime + lda #PC_GET_CLOCK Time packet + pshs u,y,x,d + IFGT Level-1 + ldu <D.DWSubAddr + ELSE + ldu >D.DWSubAddr + ENDC + beq UpdLeave in case we failed to link it, just exit + leax ,s + ldy #$0001 + jsr PIO$Write,u + leas -9,s + leax ,s + ldy #$0009 + jsr PIO$Read,u + ldy #$0000 + lda 4,x year + adda #100 + sta D.Year,y + lda 1,x month + sta D.Month,y + lda 2,x day + sta D.Day,y + lda 5,x hour + sta D.Hour,y + lda 6,x minute + sta D.Min,y + lda 7,x second + sta D.Sec,y + leas 9,s +UpdLeave puls d,x,y,u,pc + + +Init +* Check if subroutine already linked + IFGT Level-1 + ldx <D.DWSubAddr + ELSE + ldx >D.DWSubAddr + ENDC + bne leave + IFGT Level-1 + ldx <D.Proc + pshs x + ldx <D.SysPrc + stx <D.Proc + ENDC + leax subname,pcr + clra + os9 F$Link + IFGT Level-1 + puls x + stx <D.Proc + bcs leave + sty <D.DWSubAddr + ELSE + bcs leave + sty >D.DWSubAddr + ENDC + jmp ,y call initialization routine +leave rts + + emod +eom equ * + end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/modules/defsfile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,1 @@ + use ../defsfile
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/modules/kernel/defsfile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,1 @@ + use ../../defsfile
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/modules/kernel/makefile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,2 @@ +PORT = corsham +include ../../../coco1/modules/kernel/makefile
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/modules/makefile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,94 @@ +include ../port.mak + +vpath %.asm $(LEVEL1)/modules + +AFLAGS += --includedir=$(LEVEL1)/modules + +CLOCKSOFT = -DRTCSoft=1 + +DEPENDS = ./makefile +TPB = $(3RDPARTY)/booters + +BOOTERS = rel boot_cshsd +KERNEL = krn krnp2 +SYSMODS = ioman init sysgo sysgo_rom pio.sb +CLOCKS = clock clock2_cshsd + +RBF = rbf.mn rbcshsd.dr ddh0.dd h0.dd h1.dd h2.dd h3.dd + +SCF = scf.mn \ + vrn.dr \ + nil.dd \ + sc6850.dr term_sc6850.dt + +PIPE = pipeman.mn \ + piper.dr \ + pipe.dd + + +ALLOBJS = $(BOOTERS) $(KERNEL) $(SYSMODS) $(CLOCKS) $(RBF) $(SCF) $(PIPE) $(DW) + +all: $(ALLOBJS) + +# Kernel +krn krnp2: + $(CD) kernel; make $@ + $(CP) kernel/$@ . + + +sysgo_rom: sysgo.asm + $(AS) $(AFLAGS) $(ASOUT)$@ $< -DROM=1 + +# DriveWire 3 RBF descriptors +ddh0.dd: rbdesc.asm + $(AS) $< $(ASOUT)$@ $(AFLAGS) -DDD=1 -DDNum=0 + +h0.dd: rbdesc.asm + $(AS) $< $(ASOUT)$@ $(AFLAGS) -DDNum=0 + +h1.dd: rbdesc.asm + $(AS) $< $(ASOUT)$@ $(AFLAGS) -DDNum=1 + +h2.dd: rbdesc.asm + $(AS) $< $(ASOUT)$@ $(AFLAGS) -DDNum=2 + +h3.dd: rbdesc.asm + $(AS) $< $(ASOUT)$@ $(AFLAGS) -DDNum=3 + +# 6850 terminal +term_sc6850.dt: term_sc6850.asm + $(AS) $< $(ASOUT)$@ $(AFLAGS) -DHwBASE=0xE010 + +# Clocks +clock: clock.asm + $(AS) $(AFLAGS) $(ASOUT)$@ $< + +clean: + $(CD) kernel; make $@ + $(RM) $(ALLOBJS) + +showobjs: + @$(ECHO) $(ALLOBJS) + +showkernel: + @$(ECHO) $(KERNEL) + +showsysmods: + @$(ECHO) $(SYSMODS) + +showclocks: + @$(ECHO) $(CLOCKS) + +showrbf: + @$(ECHO) $(RBF) + +showscf: + @$(ECHO) $(SCF) + +showpipe: + @$(ECHO) $(PIPE) + +identify: + $(IDENT_SHORT) $(ALLOBJS) + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/modules/pio.asm Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,232 @@ +******************************************************************** +* pio - Corsham Arduino Parallel I/O Low Level Subroutine Module +* +* $Id$ +* +* Edt/Rev YYYY/MM/DD Modified by +* Comment +* ------------------------------------------------------------------ +* 1 2017/05/09 Boisy G. Pitre +* Started. +* + nam pio + ttl Corsham Arduino Parallel I/O Low Level Subroutine Module + + ifp1 + use defsfile + endc + +tylg set Sbrtn+Objct +atrv set ReEnt+rev +rev set $01 + + mod eom,name,tylg,atrv,start,0 + +name fcs /pio/ + +* PIA subroutine entry table +start bra Init + nop + bra PIARead + nop + bra PIAWrite + nop + +* Term +* +* Entry: +* U = address of device memory area +* +* Exit: +* CC = carry set on error +* B = error code +* +Term + clrb clear Carry + rts + + +* Init +* +* Entry: +* Y = address of device descriptor +* U = address of device memory area +* +* Exit: +* CC = carry set on error +* B = error code +* +* Initialize the serial device +Init +; +; Set up the data direction register for port B so that +; the DIRECTION and PSTROBE bits are output. +; + pshs d,x + ldx #PIA0Base + clr PIACTLB,x ;select DDR ...for port B + ldd #$04*256+DIRECTION|PSTROBE + stb PIADDRB,x + sta PIACTLB,x + bsr xParSetWrite + puls d,x,pc + +; Fall through to set up for writes... +; + page +;***************************************************** +; This sets up for writing to the Arduino. Sets up +; direction registers, drives the direction bit, etc. +; +; Entry: X = PIA Base +; +; All registers preserved +; +xParSetWrite pshs d + ldd #$0004 + sta PIACTLA,x ; select DDRfor port A + deca ; A $00 => $FF + sta PIADDRA,x + stb PIACTLA,x ;select data reg +; +; Set direction flag to output, clear ACK bit +; + lda #DIRECTION + sta PIAREGB,x + puls d,pc + + page +;***************************************************** +; This sets up for reading from the Arduino. Sets up +; direction registers, clears the direction bit, etc. +; +; Entry: X = PIA +; +; All registers preserved +; +xParSetRead pshs b + ldb #$04 + clr PIACTLA,x ;select DDR for port A + clr PIADDRA,x + stb PIACTLA,x ;select data reg +; +; Set direction flag to input, clear ACK bit +; + clr PIAREGB,x + puls b,pc + + page +;***************************************************** +; Entry: X = address of bytes to write +; Y = byte count +; +; All registers preserved. +; +; Write cycle: +; +; 1. Wait for other side to lower ACK. +; 2. Put data onto the bus. +; 3. Set DIRECTION and PSTROBE to indicate data +; is valid and ready to read. +; 4. Wait for ACK line to go high, indicating the +; other side has read the data. +; 5. Lower PSTROBE. +; 6. Wait for ACK to go low, indicating end of +; transfer. +; +PIAWrite pshs b,x,y,u ;save data + tfr x,u + ldx #PIA0Base + bsr xParSetWrite +Parwl22 ldb PIAREGB,x ;check status + andb #ACK + bne Parwl22 ;wait for ACK to go low + +; +; Now put the data onto the bus +; +nextbyte@ ldb ,u+ + stb PIAREGA,x +; +; Raise the strobe so the Arduino knows there is +; new data. +; + ldb PIAREGB,x + orb #PSTROBE + stb PIAREGB,x +; +; Wait for ACK to go high, indicating the Arduino has +; pulled the data and is ready for more. +; +Parwl33 ldb PIAREGB,x + andb #ACK + beq Parwl33 +; +; Now lower the strobe, then wait for the Arduino to +; lower ACK. +; + ldb PIAREGB,x + andb #~PSTROBE + stb PIAREGB,x +Parwl44 ldb PIAREGB,x + andb #ACK + bne Parwl44 + leay -1,y + bne nextbyte@ + + puls b,x,y,u,pc + + page +;***************************************************** +; Entry: X = address of buffer to hold bytes +; Y = byte count +; +; This does not have a time-out. +; +; Preserves all registers. +; +; Read cycle: +; +; 1. Wait for other side to raise ACK, indicating +; data is ready. +; 2. Read data. +; 3. Raise PSTROBE indicating data was read. +; 4. Wait for ACK to go low. +; 5. Lower PSTROBE. +; +PIARead + pshs b,x,y,u + tfr x,u + ldx #PIA0Base + bsr xParSetRead +rloop@ ldb PIAREGB,x + andb #ACK ;is their strobe high? + beq rloop@ ;nope, no data +; +; Data is available, so grab and save it. +; + ldb PIAREGA,x + stb ,u+ +; +; Now raise our strobe (their ACK), then wait for +; them to lower their strobe. +; + ldb PIAREGB,x + orb #PSTROBE + stb PIAREGB,x +Parrlp1 ldb PIAREGB,x + andb #ACK + bne Parrlp1 ;still active +; +; Lower our ack, then we're done. +; + ldb PIAREGB,x + andb #~PSTROBE + stb PIAREGB,x + leay -1,y + bne rloop@ + puls b,x,y,u,pc + + emod +eom equ * + end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/modules/rbcshsd.asm Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,317 @@ +******************************************************************** +* rbcshsd - Corsham SD driver +* +* $Id$ +* +* This driver works with the Corsham SS=50 SD/RTC Shield +* +* Edt/Rev YYYY/MM/DD Modified by +* Comment +* ------------------------------------------------------------------ +* 1 2017/05/08 Boisy G. Pitre +* Started. + + nam rbcshsd + ttl DriveWire RBF driver + +NUMRETRIES equ 8 + + ifp1 + use defsfile + endc + +NumDrvs set 4 + +tylg set Drivr+Objct +atrv set ReEnt+rev +rev set $01 +edition set 1 + + mod eom,name,tylg,atrv,start,size + + rmb DRVBEG+(DRVMEM*NumDrvs) +dcmd rmb 1 +dno rmb 1 +dssz rmb 1 +dscthi rmb 2 +dsctlo rmb 2 +resp rmb 1 +size equ . + + fcb DIR.+SHARE.+PEXEC.+PREAD.+PWRIT.+EXEC.+UPDAT. + +name fcs /rbcshsd/ + fcb edition + +start bra Init + nop + lbra Read + lbra Write + lbra GetStat + lbra SetStat + +* Term +* +* Entry: +* U = address of device memory area +* +* Exit: +* CC = carry set on error +* B = error code +* +Term + clrb + rts + +* Init +* +* Entry: +* Y = address of device descriptor +* U = address of device memory area +* +* Exit: +* CC = carry set on error +* B = error code +* +Init + IFGT Level-1 +* Perform this so we can successfully do F$Link below + ldx <D.Proc + pshs a,x + ldx <D.SysPrc + stx <D.Proc + ELSE + pshs a + ENDC + + ldb #NumDrvs + stb V.NDRV,u + leax DRVBEG,u + lda #$FF +Init2 sta DD.TOT,x invalidate drive tables + sta DD.TOT+1,x + sta DD.TOT+2,x + leax DRVMEM,x + decb + bne Init2 + +* Check if subroutine module has already been linked + IFGT LEVEL-1 + ldu <D.DWSubAddr + ELSE + ldu >D.DWSubAddr + ENDC + bne InitEx +* Link to subroutine module + clra + leax iosub,pcr + os9 F$Link + bcs InitEx + tfr y,u + IFGT LEVEL-1 + stu <D.DWSubAddr + ELSE + stu >D.DWSubAddr + ENDC +* Initialize the low level device + jsr ,u + clrb + +InitEx + IFGT Level-1 + puls a,x + stx <D.Proc +InitEx2 + rts + ELSE +InitEx2 + puls a,pc + ENDC + +* Read +* +* Entry: +* B = MSB of LSN +* X = LSB of LSN +* Y = address of path descriptor +* U = address of device memory area +* +* Exit: +* CC = carry set on error +* B = error code +* +Read + cmpx #$0000 LSN 0? + bne ReadSect branch if not + tstb LSN 0? + bne ReadSect branch if not +* At this point we are reading LSN0 + bsr ReadSect read the sector + bcs CpyLSNEx if error, exit + leax DRVBEG,u point to start of drive table + ldb <PD.DRV,y get drive number +NextDrv beq CopyLSN0 branch if terminal count + leax <DRVMEM,x else move to next drive table entry + decb decrement counter + bra NextDrv and continue +CopyLSN0 ldb #DD.SIZ get size to copy + ldy PD.BUF,y point to buffer +CpyLSNLp lda ,y+ get byte from buffer + sta ,x+ and save in drive table + decb + bne CpyLSNLp +CpyLSNEx rts + + +ReadSect + lda PD.DRV,y get drive number + cmpa #NumDrvs + blo ReadOk + coma + ldb #E$Unit + rts + +ReadOk andcc #^Carry + pshs cc,y,u + sta dno,u + lda #2 + sta dssz,u + clra + std dscthi,u + stx dsctlo,u + lda #PC_READ_LONG load A with READ opcode + sta dcmd,u + ldy #7 + leax dcmd,u + + IFGT LEVEL-1 + ldu <D.DWSubAddr + ELSE + ldu >D.DWSubAddr + ENDC + orcc #IntMasks + jsr 6,u + ldy #1 + jsr 3,u + lda ,x + cmpa #PR_SECTOR_DATA + bne ReadEr1 + +* Get 256 bytes of sector data + ldx 1,s get path descriptor ptr + ldx PD.BUF,x get buffer pointer into X + ldy #$0100 + IFGT LEVEL-1 + ldu <D.DWSubAddr + ELSE + ldu >D.DWSubAddr + ENDC + jsr 3,u + bcc ReadEx + +ReadEr1 puls cc,y,u + orcc #Carry + ldb #E$Read + rts +ReadEx puls cc,y,u,pc + + + +* Write +* +* Entry: +* B = MSB of LSN +* X = LSB of LSN +* Y = address of path descriptor +* U = address of device memory area +* +* Exit: +* CC = carry set on error +* B = error code +* +Write lda PD.DRV,y + cmpa #NumDrvs + blo WriteSect + comb set Carry + ldb #E$Unit + rts + +WriteSect andcc #^Carry + pshs cc,y,u + sta dno,u + lda #2 + sta dssz,u + clra + std dscthi,u + stx dsctlo,u + lda #PC_WRITE_LONG load A with WRITE opcode + sta dcmd,u + ldy #7 + leax dcmd,u + + IFGT LEVEL-1 + ldu <D.DWSubAddr + ELSE + ldu >D.DWSubAddr + ENDC + orcc #IntMasks + jsr 6,u +* Write 256 bytes of sector data + ldx 1,s get path descriptor ptr + ldx PD.BUF,x get buffer pointer into X + ldy #$0100 + jsr 6,u + + ldx 1,s get path descriptor ptr + leax resp,x + ldy #1 + jsr 3,u + lda ,x + cmpa #RACK + beq WriteEx + +* read error byte but ignore + ldy #1 + jsr 3,u + +WriteEr1 puls cc,y,u + orcc #Carry + ldb #E$Write + rts +WriteEx + puls cc,y,u,pc + +* SetStat +* +* Entry: +* R$B = function code +* Y = address of path descriptor +* U = address of device memory area +* +* Exit: +* CC = carry set on error +* B = error code +* +SetStat +* Size optimization + + +* GetStat +* +* Entry: +* R$B = function code +* Y = address of path descriptor +* U = address of device memory area +* +* Exit: +* CC = carry set on error +* B = error code +* +GetStat + rts + +iosub fcs /pio/ + + emod +eom equ * + end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/modules/rbdesc.asm Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,92 @@ +******************************************************************** +* rbdesc - Device Descriptor Template +* +* $Id$ +* +* Edt/Rev YYYY/MM/DD Modified by +* Comment +* 1/1 2013-12/10 Gene heskett +* Raised default SAS to $10, shortens FD.SEG +* usage for longer files +* ------------------------------------------------------------------ + + nam rbdesc + ttl Device Descriptor Template + +* Disassembled 98/08/23 17:09:41 by Disasm v1.6 (C) 1988 by RML + + ifp1 + use defsfile + endc + +tylg set Devic+Objct +atrv set ReEnt+rev +rev set $01 + + IFNDEF DNum +DNum set 0 + ENDC + IFNE D35 +Type set TYP.CCF+TYP.3 + ELSE +Type set TYP.CCF+TYP.5 + ENDC + IFNDEF Density +Density set DNS.MFM + ENDC + IFNDEF Step +Step set STP.6ms + ENDC + IFNDEF Cyls +Cyls set 35 + ENDC + IFNDEF Sides +Sides set 1 + ENDC +Verify set 1 + IFNDEF SectTrk +SectTrk set 18 + ENDC + IFNDEF SectTrk0 +SectTrk0 set 18 + ENDC + IFNDEF Interlv +Interlv set 3 + ENDC + IFNDEF SAS +SAS set 10 + ENDC + + mod eom,name,tylg,atrv,mgrnam,drvnam + + fcb DIR.!SHARE.!PEXEC.!PWRIT.!PREAD.!EXEC.!UPDAT. mode byte + fcb HW.Page extended controller address + fdb $FF40 physical controller address + fcb initsize-*-1 initalization table size + fcb DT.RBF device type:0=scf,1=rbf,2=pipe,3=scf + fcb DNum drive number + fcb Step step rate + fcb Type drive device type + fcb Density media density:0=single,1=double + fdb Cyls number of cylinders (tracks) + fcb Sides number of sides + fcb Verify verify disk writes:0=on + fdb SectTrk # of sectors per track + fdb SectTrk0 # of sectors per track (track 0) + fcb Interlv sector interleave factor + fcb SAS minimum size of sector allocation +initsize equ * + + IFNE DD +name fcs /DD/ + ELSE +name fcc /H/ + fcb '0+DNum+$80 + ENDC +mgrnam fcs /RBF/ +drvnam fcs /rbcshsd/ + + emod +eom equ * + end +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/modules/rel.asm Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,263 @@ +******************************************************************* +* REL - Relocation routine +* +* $Id$ +* +* This module MUST occupy the last 256 bytes of ROM ($FF00-$FFFF) +* due to the way the Corsham board is designed. +* +* Edt/Rev YYYY/MM/DD Modified by +* Comment +* ------------------------------------------------------------------ +* 1 2017/05/08 Boisy G. Pitre +* Created for Corsham 6809 +* + + nam REL + ttl Relocation routine + + IFP1 + use defsfile + ENDC + +tylg set Systm+Objct +atrv set ReEnt+rev +rev set $05 +edition set 5 + +Begin mod eom,name,tylg,atrv,start,size + + org 0 +size equ . REL doesn't require any memory + +name fcs /REL/ + fcb edition + +************************************************************************* +* Entry point for Level 1 + +Start +* Initialize UART + ldx #UARTBase POINT TO CONTROL PORT ADDRESS + lda #3 RESET ACIA PORT CODE + sta ,x STORE IN CONTROL REGISTER + lda #$11 SET 8 DATA, 2 STOP AN 0 PARITY + sta ,x STORE IN CONTROL REGISTER + tst 1,x ANYTHING IN DATA REGISTER? + +* INITIALIZE DAT RAM --- LOADS $F-$0 IN LOCATIONS $0-$F +* OF DAT RAM, THUS STORING COMPLEMENT OF MSB OF ADDRESS +* IN THE DAT RAM. THE COMPLEMENT IS REQUIRED BECAUSE THE +* OUTPUT OF IC11, A 74S189, IS THE INVERSE OF THE DATA +* STORED IN IT. +; +; Also note that the upper nibble contains the non-inverted +; bank number for extended addressing. This loop sets up all +; translations to point to block 0, which is good. +; +InitDAT ldx #DATREGS point to DAT RAM + lda #$0F get complement of zero +datlp@ sta ,x+ STORE & POINT TO NEXT RAM LOCATION + deca GET COMP. VALUE FOR NEXT LOCATION + bne datlp@ ALL 16 LOCATIONS INITIALIZED ? + + +* NOTE: IX NOW CONTAINS $0000, DAT RAM IS NO LONGER +* ADDRESSED, AND LOGICAL ADDRESSES NOW EQUAL +* PHYSICAL ADDRESSES. +TSTPAT equ $55AA TEST PATTERN + + lda #$F0 + sta ,x STORE $F0 AT $FFFF + ldx #$D0A0 ASSUME RAM TO BE AT $D000-$DFFF + ldy #TSTPAT LOAD TEST DATA PATTERN INTO "Y" +tstram@ ldu ,x SAVE DATA FROM TEST LOCATION + sty ,x STORE TEST PATTERN AT $D0A0 + cmpy ,x IS THERE RAM AT THIS LOCATION ? + beq CNVADR IF MATCH THERE'S RAM, SO SKIP + leax -$1000,x ELSE POINT 4K LOWER + cmpx #$F0A0 DECREMENTED PAST ZER0 YET ? + bne tstram@ IF NOT CONTINUE TESTING FOR RAM + bra InitDAT ELSE START ALL OVER AGAIN + +* THE FOLLOWING CODE STORES THE COMPLEMENT OF +* THE MS CHARACTER OF THE FOUR CHARACTER HEX +* ADDRESS OF THE FIRST 4K BLOCK OF RAM LOCATED +* BY THE ROUTINE "TSTRAM" INTO THE DAT RAM. IT +* IS STORED IN RAM IN THE LOCATION THAT IS +* ADDRESSED WHEN THE PROCESSOR ADDRESS IS $D---, +* THUS IF THE FIRST 4K BLOCK OF RAM IS FOUND +* WHEN TESTING LOCATION $70A0, MEANING THERE +* IS NO RAM PHYSICALLY ADDRESSED IN THE RANGE +* $8000-$DFFF, THEN THE COMPLEMENT OF THE +* "7" IN THE $70A0 WILL BE STORED IN +* THE DAT RAM. THUS WHEN THE PROCESSOR OUTPUTS +* AN ADDRESS OF $D---, THE DAT RAM WILL RESPOND +* BY RECOMPLEMENTING THE "7" AND OUTPUTTING THE +* 7 ONTO THE A12-A15 ADDRESS LINES. THUS THE +* RAM THAT IS PHYSICALLY ADDRESSED AT $7--- +* WILL RESPOND AND APPEAR TO THE 6809 THAT IT +* IS AT $D--- SINCE THAT IS THE ADDRESS THE +* 6809 WILL BE OUTPUTING WHEN THAT 4K BLOCK +* OF RAM RESPONDS. + + +CNVADR stu ,x RESTORE DATA AT TEST LOCATION + tfr x,d PUT ADDR. OF PRESENT 4K BLOCK IN D + coma COMPLEMENT MSB OF THAT ADDRESS + lsra PUT MS 4 BITS OF ADDRESS IN + lsra LOCATION D0-D3 TO ALLOW STORING + lsra IT IN THE DYNAMIC ADDRESS + lsra TRANSLATION RAM. + sta $FFFD STORE XLATION FACTOR IN DAT "D" + + +* THE FOLLOWING CHECKS TO FIND THE REAL PHYSICAL ADDRESSES +* OF ALL 4K BLKS OF RAM IN THE SYSTEM. WHEN EACH 4K BLK +* OF RAM IS LOCATED, THE COMPLEMENT OF IT'S REAL ADDRESS +* IS THEN STORED IN A "LOGICAL" TO "REAL" ADDRESS XLATION +* TABLE THAT IS BUILT FROM $DFD0 TO $DFDF. FOR EXAMPLE IF +* THE SYSTEM HAS RAM THAT IS PHYSICALLY LOCATED (WIRED TO +* RESPOND) AT THE HEX LOCATIONS $0--- THRU $F---.... + +* 0 1 2 3 4 5 6 7 8 9 A B C D E F +* 4K 4K 4K 4K 4K 4K 4K 4K -- 4K 4K 4K 4K -- -- -- + +* ....FOR A TOTAL OF 48K OF RAM, THEN THE TRANSLATION TABLE +* CREATED FROM $DFD0 TO $DFDF WILL CONSIST OF THE FOLLOWING.... + +* 0 1 2 3 4 5 6 7 8 9 A B C D E F +* 0F 0E 0D 0C 0B 0A 09 08 06 05 00 00 04 03 F1 F0 + + +* HERE WE SEE THE LOGICAL ADDRESSES OF MEMORY FROM $0000-$7FFF +* HAVE NOT BEEN SELECTED FOR RELOCATION SO THAT THEIR PHYSICAL +* ADDRESS WILL = THEIR LOGICAL ADDRESS; HOWEVER, THE 4K BLOCK +* PHYSICALLY AT $9000 WILL HAVE ITS ADDRESS TRANSLATED SO THAT +* IT WILL LOGICALLY RESPOND AT $8000. LIKEWISE $A,$B, AND $C000 +* WILL BE TRANSLATED TO RESPOND TO $9000,$C000, AND $D000 +* RESPECTIVELY. THE USER SYSTEM WILL LOGICALLY APPEAR TO HAVE +* MEMORY ADDRESSED AS FOLLOWS.... + +* 0 1 2 3 4 5 6 7 8 9 A B C D E F +* 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K -- -- 4K 4K -- -- + + + ldy #LRARAM ;POINT TO LOGICAL/REAL ADDR. TABLE + sta 13,y ;STORE $D--- XLATION FACTOR AT $DFDD + clr 14,y ;CLEAR $DFDE + lda #$F0 ;DESTINED FOR IC8 AN MEM EXPANSION ? + sta 15,y ;STORE AT $DFDF + lda #$0C ;PRESET NUMBER OF BYTES TO CLEAR +CLRLRT clr a,y ;CLEAR $DFDC THRU $DFD0 + deca ;. 1 FROM BYTES LEFT TO CLEAR + bpl CLRLRT ;CONTINUE IF NOT DONE CLEARING +FNDRAM leax -$1000,x ;POINT TO NEXT LOWER 4K OF RAM + cmpx #$F0A0 ;TEST FOR DECREMENT PAST ZERO + beq FINTAB ;SKIP IF FINISHED + ldu ,x ;SAVE DATA AT CURRENT TEST LOCATION + ldy #TSTPAT ;LOAD TEST DATA PATTERN INTO Y REG. + sty ,x ;STORE TEST PATT. INTO RAM TEST LOC. + cmpy ,x ;VERIFY RAM AT TEST LOCATION + bne FNDRAM ;IF NO RAM GO LOOK 4K LOWER + stu ,x ;ELSE RESTORE DATA TO TEST LOCATION + ldy #LRARAM ;POINT TO LOGICAL/REAL ADDR. TABLE + tfr x,d ;PUT ADDR. OF PRESENT 4K BLOCK IN D + lsra ;PUT MS 4 BITS OF ADDR. IN LOC. D0-D3 + lsra ;TO ALLOW STORING IT IN THE DAT RAM. + lsra + lsra + tfr a,b ;SAVE OFFSET INTO LRARAM TABLE + eora #$0F ;INVERT MSB OF ADDR. OF CURRENT 4K BLK + sta b,y ;SAVE TRANSLATION FACTOR IN LRARAM TABLE + bra FNDRAM ;GO TRANSLATE ADDR. OF NEXT 4K BLK +FINTAB lda #$F1 ;DESTINED FOR IC8 AND MEM EXPANSION ? + ldy #LRARAM ;POINT TO LRARAM TABLE + sta 14,y ;STORE $F1 AT $DFCE + +* THE FOLLOWING CHECKS TO SEE IF THERE IS A 4K BLK OF +* RAM LOCATED AT $C000-$CFFF. IF NONE THERE IT LOCATES +* THE NEXT LOWER 4K BLK AN XLATES ITS ADDR SO IT +* LOGICALLY RESPONDS TO THE ADDRESS $C---. + + + lda #$0C ;PRESET NUMBER HEX "C" +FINDC ldb a,y ;GET ENTRY FROM LRARAM TABLE + bne FOUNDC ;BRANCH IF RAM THIS PHYSICAL ADDR. + deca ;ELSE POINT 4K LOWER + bpl FINDC ;GO TRY AGAIN + bra XFERTF +FOUNDC clr a,y ;CLR XLATION FACTOR OF 4K BLOCK FOUND + stb $C,y ;GIVE IT XLATION FACTOR MOVING IT TO $C--- + +* THE FOLLOWING CODE ADJUSTS THE TRANSLATION +* FACTORS SUCH THAT ALL REMAINING RAM WILL +* RESPOND TO A CONTIGUOUS BLOCK OF LOGICAL +* ADDRESSES FROM $0000 AND UP.... + + clra ;START AT ZERO + tfr y,x ;START POINTER "X" START OF "LRARAM" TABLE. +COMPRS ldb a,y ;GET ENTRY FROM "LRARAM" TABLE + beq PNTNXT ;IF IT'S ZER0 SKIP + clr a,y ;ELSE ERASE FROM TABLE + stb ,x+ ;AND ENTER ABOVE LAST ENTRY- BUMP +PNTNXT inca ;GET OFFSET TO NEXT ENTRY + cmpa #$0C ;LAST ENTRY YET ? + blt COMPRS + +* THE FOLLOWING CODE TRANSFER THE TRANSLATION +* FACTORS FROM THE LRARAM TABLE TO IC11 ON +* THE MP-09 CPU CARD. + +XFERTF ldx #DATREGS ;POINT TO DAT RAM + ldb #$10 ;GET NO. OF BYTES TO MOVE +FETCH lda ,y+ ;GET BYTE AND POINT TO NEXT + sta ,x+ ;POKE XLATION FACTOR IN IC11 + decb ;SUB 1 FROM BYTES TO MOVE + bne FETCH ;CONTINUE UNTIL 16 MOVED + +* Initialization is complete at this point +* Jump into Kernel at $F011 + jmp $F011 jump into Krn + +* Entry +* A = character to output +CharOut pshs b SAVE A ACCUM AND IX +fetch@ ldb UARTBase FETCH PORT STATUS + bitb #2 TEST TDRE, OK TO XMIT ? + beq fetch@ IF NOT LOOP UNTIL RDY + sta UARTBase+1 XMIT CHAR. + puls b,pc restore and leave + +* Entry +* X = nil terminated string +StringOut pshs a,x +loop@ lda ,x+ + beq done@ + bsr CharOut + bra loop@ +done@ puls a,x,pc + + fill $39,$100-*-EOMSize + +EOMTop EQU * + +* I/O routines jump table (known locations) +LFFE9 fdb $FF00+CharOut +LFFEB fdb $FF00+StringOut + + EMOD +eom EQU * + + fdb $0000 +Vectors fdb $0100 SWI3 + fdb $0103 SWI2 + fdb $010F FIRQ + fdb $010C IRQ + fdb $0106 SWI + fdb $0109 NMI + fdb $FF00+Start start of REL + +EOMSize equ *-EOMTop + + end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/port.mak Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,8 @@ +PORT = corsham +MACHINE = Corsham 6809 +CPU = 6809 +LEVEL = 1 +TELNET_PORT = 6801 +HTTPD_PORT = 8801 + +include $(NITROS9DIR)/rules.mak
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/startup Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,6 @@ +* Echo welcome message +echo * Welcome to NitrOS-9 Level 1 * +echo * on the Corsham 6809 SS-50 * +echo +date -t +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/corsham/sys/makefile Tue May 16 23:20:18 2017 +0200 @@ -0,0 +1,36 @@ +include ../port.mak + +vpath %.hp $(LEVEL1)/sys + +DEPENDS = ./makefile + +SYSFILES = ../../sys/errmsg ../../sys/motd ../../sys/password inetd.conf +HELPFILES = asm.hp attr.hp backup.hp binex.hp build.hp chd.hp \ + chx.hp cmp.hp cobbler.hp config.hp copy.hp cputype.hp date.hp \ + dcheck.hp debug.hp ded.hp deiniz.hp del.hp deldir.hp devs.hp \ + dir.hp dirsort.hp disasm.hp display.hp dmode.hp dsave.hp dump.hp echo.hp \ + edit.hp error.hp ex.hp exbin.hp format.hp free.hp gfx.hp \ + help.hp ident.hp iniz.hp inkey.hp irqs.hp kill.hp link.hp \ + list.hp load.hp login.hp makdir.hp \ + mdir.hp megaread.hp merge.hp mpi.hp mfree.hp os9gen.hp \ + padrom.hp park.hp procs.hp prompt.hp pwd.hp pxd.hp \ + rename.hp save.hp setime.hp \ + setpr.hp shell.hp sleep.hp tee.hp tmode.hp touch.hp tsmon.hp \ + tuneport.hp unlink.hp verify.hp xmode.hp +HELPMSG = helpmsg +ALLOBJS = $(SYSFILES) $(HELPMSG) + + +all: $(ALLOBJS) $(DEPENDS) + +inetd.conf: $(LEVEL1)/sys/inetd.conf + @sed -e 's/%TELNET_PORT%/$(TELNET_PORT)/' -e 's/%HTTPD_PORT%/$(HTTPD_PORT)/' $^ > $@ + +helpmsg: $(HELPFILES) + $(MERGE) $^ > $@ + +clean: + $(RM) $(HELPMSG) inetd.conf + +showobjs: + @$(ECHO) $(ALLOBJS)
--- a/level1/makefile Tue May 16 19:34:56 2017 +0200 +++ b/level1/makefile Tue May 16 23:20:18 2017 +0200 @@ -1,6 +1,6 @@ include $(NITROS9DIR)/rules.mak -dirs = coco1 coco1_6309 deluxe coco2 coco2_6309 coco2b tano d64 dalpha atari mc09 +dirs = coco1 coco1_6309 deluxe coco2 coco2_6309 coco2b tano d64 dalpha atari mc09 corsham ifdef PORTS dirs = $(PORTS) endif
--- a/level1/modules/clock.asm Tue May 16 19:34:56 2017 +0200 +++ b/level1/modules/clock.asm Tue May 16 23:20:18 2017 +0200 @@ -154,6 +154,77 @@ jsr ,y call init entry point of Clock2 * Initialize clock hardware + IFNE corsham +* Corsham SS-50 6809 board -- uses the Arduino as a clock source +* Timer values: +* 0 = disable timer interrupts +* 1 = 10 ms +* 2 = 20 ms +* 3 = 30 ms +* 4 = 40 ms +* 5 = 50 ms +* 6 = 100 ms +* 7 = 250 ms +* 8 = 500 ms +* 9 = 1000 ms + + pshs d,cc + +* Check if subroutine module has already been linked + IFGT LEVEL-1 + ldu <D.DWSubAddr + ELSE + ldu >D.DWSubAddr + ENDC +* The following code is commented because the pio subroutine module has already +* been linked and its entry point stored prior to us getting here. +* bne SetTimer +* Link to subroutine module +* clra +* leax iosub,pcr +* os9 F$Link +* bcs ClkEx +* tfr y,u +* IFGT LEVEL-1 +* stu <D.DWSubAddr +* ELSE +* stu >D.DWSubAddr +* ENDC +* Initialize the low level device +* jsr ,u + + +SetTimer + orcc #IntMasks + ldd #CSETIMR*256+$02 + std 1,s +* Tell Arduino to generate timer interrupts + leax 1,s + ldy #2 + jsr 6,u + ldy #1 + jsr 3,u + lda ,x + cmpa #RACK + beq SETIM1 + ldy #1 + jsr 3,u read error code + bra ClkEx + +SETIM1 + +* Tell PIA to enable interrupts + ldx #PIA0Base + lda 3,x + ora #$01 *enable interrupts + sta 3,x + lda 2,x *clear pending ints + +ClkEx + puls cc,d,pc +*iosub fcs /pio/ + + ELSE IFNE atari IFNE USENMI lda #$40 @@ -196,6 +267,7 @@ lda 2,x clear possible pending PIA0 VBORD IRQ puls cc,pc recover IRQ enable status and return ENDC + ENDC * * Clock IRQ Entry Point @@ -204,6 +276,12 @@ SvcIRQ clra tfr a,dp set direct page to zero + IFNE corsham + tst PIA0Base+3 + bmi ClearInt it's a clock interrupt -- clear it + jmp [>D.SvcIRQ] else service other possible IRQ +ClearInt tst PIA0Base+2 clear clock interrupt by reading register + ELSE IFNE atari IFNE USENMI sta NMIRES clear NMI interrupt @@ -230,6 +308,7 @@ jmp [>D.SvcIRQ] else service other possible IRQ L0032 tst PIA0Base+2 clear interrupt ENDC + ENDC dec <D.Tick decrement tick counter bne L007F go around if not zero ldb <D.Sec get minutes/seconds
--- a/level1/modules/init.asm Tue May 16 19:34:56 2017 +0200 +++ b/level1/modules/init.asm Tue May 16 23:20:18 2017 +0200 @@ -159,7 +159,11 @@ IFNE coco3fpga fcc "Gary Becker's Coco3FPGA" ELSE + IFNE corsham + fcc "Corsham 6809" + ELSE fcc "Unknown Machine" + ENDC match IFNE corsham ENDC match IFNE coco3fpga ENDC match IFNE mc09 ENDC match IFNE atari
--- a/level1/modules/kernel/krn.asm Tue May 16 19:34:56 2017 +0200 +++ b/level1/modules/kernel/krn.asm Tue May 16 23:20:18 2017 +0200 @@ -182,9 +182,15 @@ ldx #$FFFF stx <D.BTHI ELSE + IFNE corsham + ldx #Bt.Start + ldy #Bt.Start+Bt.Size-1 + ELSE +* CoCo ldy #Bt.Start+Bt.Size ENDC - + ENDC + lbsr ValMods * Atari: look for more modules at $D800-$F3FF @@ -258,9 +264,18 @@ ldb #%10000000 stb 1,x mark $0800-$08FF as allocated ELSE -* For all (other) platforms, memory $0000-$04FF is used by the system + IFNE corsham +* Corsham needs $0000-$04FF and $E000-$EFFF reserved ldb #%11111000 - stb ,x + stb ,x mark $0000-$04FF as allocated + ldb #%11111111 + stb $1C,x mark $E000-$E7FF I/O area as allocated + stb $1D,x mark $E800-$EFFF I/O area as allocated + ELSE +* CoCo needs $0000-$04FF reserved + ldb #%11111000 + stb ,x mark $0000-$04FF as allocated + ENDC ENDC * For all platforms exclude high memory as defined (earlier) by D.MLIM @@ -968,20 +983,30 @@ P2Nam fcs /krnp2/ - emod -eom equ * - -Vectors fdb SWI3 SWI3 - fdb SWI2 SWI2 - fdb DUMMY FIRQ - fdb SVCIRQ IRQ - fdb SWI SWI - fdb SVCNMI NMI - IFNE atari - fdb $F3FE-(*-OS9Cold) - ENDC - -eomem equ * - end +EOMTop EQU * + + IFEQ corsham + emod +eom equ * + ENDC + + IFNE atari + fdb $F3FE-(*-OS9Cold) + ENDC + +Vectors fdb SWI3 SWI3 + fdb SWI2 SWI2 + fdb DUMMY FIRQ + fdb SVCIRQ IRQ + fdb SWI SWI + fdb SVCNMI NMI + + IFNE corsham + emod +eom equ * + ENDC +EOMSize equ *-EOMTop + + end
--- a/level1/modules/sysgo.asm Tue May 16 19:34:56 2017 +0200 +++ b/level1/modules/sysgo.asm Tue May 16 23:20:18 2017 +0200 @@ -109,7 +109,7 @@ * Default time packet DefTime dtb - IFEQ atari + IFEQ atari+corsham IFEQ Level-1 * BASIC reset code (CoCo port only) BasicRst fcb $55 @@ -203,7 +203,7 @@ L0125 equ * pshs u,y - IFEQ atari + IFEQ atari+corsham IFEQ Level-1 * Setup BASIC code (CoCo port only) leax >BasicRst,pcr @@ -242,7 +242,7 @@ IFEQ ROM * Fork shell startup here - IFEQ atari + IFEQ atari+corsham * Added 12/14/03: If SHIFT is held down, startup is not run (CoCo only) lda #$01 standard output ldb #SS.KySns