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changeset 3150:37737e5ec640

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Add coco3fpga RAM disk and RTC driver Added clock2_coco3fpga.as to level1/modules. Added ramd_coco3fpga.asm & r0_ramd_coco3fpga.asm to level2/modules. Build them on level2/coco3. Added definitions to "coco3/modules/makefile" to build 'ramd_coco3fpga.dr", "r0_ramd_cocofga.dd" & "clock2_coco3fpga".
author Bill Pierce <merlinious999@gmail.com>
date Mon, 06 Feb 2017 22:25:15 +0100
parents afd0f7d9b514
children d5c884d63e53
files level1/modules/clock2_coco3fpga.asm level2/coco3/modules/makefile level2/modules/ramd_coco3fpga.asm level2/modules/ramddesc_coco3fpga.asm
diffstat 4 files changed, 501 insertions(+), 2 deletions(-) [+]
line wrap: on
line diff
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/level1/modules/clock2_coco3fpga.asm	Mon Feb 06 22:25:15 2017 +0100
@@ -0,0 +1,192 @@
+********************************************************************
+* Clock2 - Coco3FPGA Analog Board RTC Driver
+* for the Maxim Integrated DS3231 RTC
+* Coco3FPGA ONLY!
+*
+* $Id$
+*
+* Edt/Rev  YYYY/MM/DD  Modified by
+* Comment
+* ------------------------------------------------------------------
+*   1      2004/08/18  Boisy G. Pitre
+* Separated clock2 modules for source clarity.
+*
+*   2      2017/01/21  Robert Gault
+* Modified clock2_elim.asm to work with the DS3231 on the Coco3FPGA
+*
+*   3      2017/01/23  Gary Becker
+* Corrected the timing of the Read/Write activation routines
+*
+*   4      2017/01/23  Robert Gault
+* Corrected a bug in the Setime routine and added a "stpreg" routine
+*
+*   5      2017/01/24  Bill Pierce
+* Removed erronius "stpreg" routine, cleaned up code, re-assembled, IT WORKS!
+
+         nam   Clock2    
+         ttl   Coco3FPGA Analog Board RTC Driver
+
+         ifp1            
+         use   defsfile
+         endc            
+
+tylg     set   Sbrtn+Objct
+atrv     set   ReEnt+rev
+rev      set   $00
+edition  set   4
+
+* All bits not specified must be set to 0!
+RTC.sec  equ   $00        0-59
+RTC.min  equ   $01        0-59
+RTC.hr   equ   $02        bit 6 12/24, bit5 PM/AM, or 20hr, bit4 10hr, bit3-0 hr:0-23
+RTC.day  equ   $03        bit 2-0: 1-7
+RTC.date equ   $04        bit5-4 10 date, bit 3-0 date: 1-31
+RTC.mn   equ   $05        bit4 10 mn, bit3-0 mn
+RTC.yr   equ   $06        bit7-4 10yr, bit3-0 yr
+RTC.base equ   $FF80
+RTC.data equ   $FF81      data I/O
+RTC.cmd  equ   $FF82      $D1=read, $D0=write
+RTC.adr  equ   $FF83      indicates 00h-06h see above
+RTC.tog  equ   RTC.base   set 1 then 0
+RTC.stat equ   RTC.base   wait for $80 to show ready
+
+         mod   eom,name,tylg,atrv,JmpTable,RTC.base
+
+name     fcs   "Clock2"
+         fcb   edition
+
+JmpTable                 
+         lbra  INIT
+         bra   GetTime
+         nop
+         lbra  SetTime
+		 lbra  GetSta
+		 lbra  SetSta
+		 lbra  TERM
+
+GetTime  ldx   M$Mem,pcr  get RTC base address from fake memory requirement
+         ldd   #$D106     read and year
+         sta   2,x
+         bsr   rdreg
+         lda   1,x        get year
+         bsr   bcd2hex
+         sta   <D.Year   
+         ldb   #5         month register address
+         bsr   rdreg
+         lda   1,x
+         anda  #%11111    keep only month
+         bsr   bcd2hex       
+         sta   <D.Month  
+         ldb   #4         day of month register address
+         bsr   rdreg
+         lda   1,x
+         bsr   bcd2hex       
+         sta   <D.Day    
+         ldb   #2         hour register address
+         bsr   rdreg
+         lda   1,x
+         anda  #%111111   assume 24hr clock
+         pshs  a
+         anda  #%11111    limit to 19
+         bsr   bcd2hex
+         puls  b          recover original time
+         andb  #%100000   test for 20+
+         beq   no20
+         adda  #20
+no20     sta   <D.Hour   
+         ldb   #1         minute register address
+         bsr   rdreg
+         lda   1,x
+         bsr   bcd2hex
+         sta   <D.Min    
+         clrb             second register address
+         bsr   rdreg
+         lda   1,x
+         bsr   bcd2hex
+         sta   <D.Sec    
+UpdTExit rts             
+
+rdreg    stb   3,x        set mode
+         ldb   #1         activate
+         stb   ,x
+LP1      lda   ,x         Done yet?
+         bmi   LP1        No, loop
+         clr   ,x         Clear for activation
+LP2      lda   ,x         get status
+         anda  #$80
+         beq   LP2      Update In Progress, loop
+         rts
+
+* Convert Bitcode to Hex
+bcd2hex  pshs  b
+         tfr   a,b	copy the bcd number
+         andb  #15	keep the lowest digit
+         pshs  b        save it
+         anda  #$F0
+         ldb   #160
+         mul            times 10
+         adda  ,s+      add partials
+         puls  b,pc
+
+SetTime  pshs  cc         save interrupt status
+         orcc  #IntMasks  disable IRQs
+         ldx   M$Mem,pcr  get RTC base address from fake memory requirement
+         ldd   #$D006     write and year
+         sta   2,x
+         ldy   #D.Time    point [Y] to time variables in DP
+         lda   ,y+        get year
+         bsr   hex2bcd
+         sta   1,x
+         bsr   rdreg
+         lda   ,y+        month
+         bsr   hex2bcd
+         sta   1,x
+         ldb   #5         month
+         bsr   rdreg
+         lda   ,y+        day
+         bsr   hex2bcd
+         sta   1,x
+         ldb   #4         day
+         bsr   rdreg
+         lda   ,y+        hour
+         bsr   hex2bcd
+         sta   1,x
+         ldb   #2         hour
+         bsr   rdreg
+         lda   ,y+        minute
+         bsr   hex2bcd
+         sta   1,x
+         ldb   #1         minute
+         bsr   rdreg
+         lda   ,y         sec
+         sta   1,x
+         clrb             sec = 0
+         bsr  rdreg
+         puls  cc         Recover IRQ status
+         rts
+
+* Convert Hex to Bitcode
+hex2bcd  pshs  b
+         ldb   #$FF
+lp10     incb
+         suba  #10
+         bcc   lp10
+         adda  #10
+         lslb
+         lslb
+         lslb
+         lslb
+         pshs  b
+         adda  ,s+
+         puls  b,pc
+
+INIT     equ   *
+GetSta   equ   *
+SetSta   equ   *
+TERM     equ   *
+         rts
+
+         emod            
+eom      equ   *         
+         end             
+
--- a/level2/coco3/modules/makefile	Sat Feb 04 18:55:39 2017 +0100
+++ b/level2/coco3/modules/makefile	Mon Feb 06 22:25:15 2017 +0100
@@ -14,6 +14,7 @@
 CLOCKSOFT       = -DRTCSoft=1
 CLOCKMESSEMU    = -DRTCMessEmu=1
 CLOCKJVEMU      = -DRTCJVEmu=1
+CLOCKCOCO3FPGA  = -DRTCCoco3CPGA=1
 TC3FLAGS        = $(AFLAGS) -DTC3=1 $(FLAGS)
 IDEFLAGS        = $(AFLAGS) -DIDE=1 $(FLAGS)
 SDFLAGS         = $(AFLAGS) -DCOCOSDC=1 -DITTYP=128 $(FLAGS)
@@ -31,7 +32,7 @@
 CLOCKS		= clock_60hz clock_50hz \
 		clock2_elim clock2_disto2 clock2_disto4 clock2_bnb \
 		clock2_smart clock2_harris clock2_cloud9 clock2_soft \
-		clock2_jvemu clock2_messemu clock2_dw
+		clock2_jvemu clock2_messemu clock2_dw clock2_coco3fpga
 
 RBF		= rbf.mn \
 		rbdw.dr dwio.sb dwio_becker.sb dwio_arduino.sb \
@@ -49,7 +50,8 @@
 		dds0_tc3.dd s0_tc3.dd s1_tc3.dd s2_tc3.dd s3_tc3.dd s4_tc3.dd \
 		s5_tc3.dd s6_tc3.dd sh_tc3.dd \
 		ddsd0_cocosdc.dd sd0_cocosdc.dd sd1_cocosdc.dd \
-		llcoco3fpga.dr ddsd0_coco3fpga.dd sd0_coco3fpga.dd sd1_coco3fpga.dd
+		llcoco3fpga.dr ddsd0_coco3fpga.dd sd0_coco3fpga.dd sd1_coco3fpga.dd \
+		ramd_coco3fpga.dr r0_ramd_coco3fpga.dd
 
 SCF		= scf.mn \
 		vtio.dr vrn.dr scbbp.dr scbbt.dr scdwp.dr sspak.dr sc6551.dr \
@@ -257,6 +259,10 @@
 ddr0_192k.dd: r0.asm
 	$(AS) $< $(ASOUT)$@ $(AFLAGS) -DRAMSize=192 -DDD=1
 
+# Coco3fpga ramd descriptors
+r0_ramd_coco3fpga.dd: ramddesc_coco3fpga.asm
+	$(AS) $< $(ASOUT)$@ $(AFLAGS)
+
 # DriveWire SCF descriptors
 term_scdwv.dt: scdwvdesc.asm
 	$(AS) $< $(ASOUT)$@ $(AFLAGS) -DAddr=0
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/level2/modules/ramd_coco3fpga.asm	Mon Feb 06 22:25:15 2017 +0100
@@ -0,0 +1,217 @@
+********************************************************************
+* RAMD SDRAM Disk Driver for CoCo3FPGA
+*
+* $Id: ramd.asm,v 1.0 2016/12/09 14:52:42 gbecker Exp $
+*
+* Ed.    Comments                                       Who YY/MM/DD
+* ------------------------------------------------------------------
+*  1     Initial driver                         Gary Becker 16/12/09
+*
+*  2     Updated to conform to NitrOS9 Repo     Bill Pierce 17/02/04
+*
+
+*   $FF84: SDRAM Control Register (Write)
+RAMDCON	equ	$00
+* Bit  Signal
+* 0    R/W
+*
+*   $FF84: Disk Flag (Read)
+RAMDSTA	equ	$00
+* Bit  Signal
+*  7   Operation Finished
+*  0   R/W
+*   $FF85-$FF86: DATA (Read / Write)
+RAMDDAT	equ	$01
+*
+*   $FF87-88: Block Address
+RAMDADD	equ	$03
+*
+N.Drives	equ	1	number of drives to support
+*
+* Command equates
+*
+*
+	nam	RAMD
+	ttl	os9 device driver
+
+	use	os9.d
+	use	rbf.d
+	use	coco.d
+
+tylg	set	Drivr+Objct
+atrv	set	ReEnt+rev
+rev	set	$01
+
+	org	0
+	mod	eom,name,tylg,atrv,start,size
+	fcb	$ff
+
+u0000	rmb	DRVBEG+(DRVMEM*N.Drives)
+
+size	equ	.
+
+	fcb	$FF		This byte is the driver permissions
+name	fcs	/RAMD/
+	fcb	1		edition #1
+
+start	bra	INIT		3 bytes per entry to keep RBF happy
+	nop
+	bra	READ
+	nop
+	bra	WRITE
+	nop
+	bra	GETSTA
+	nop
+	bra	SETSTA
+	nop
+	bra	TERM
+	nop
+
+* Read
+*
+* Entry:
+*	B = MSB of LSN
+*	X = LSB of LSN
+*	Y = address of path descriptor
+*	U = address of device memory area
+*
+* Exit:
+*	CC = carry set on error
+*	B = error code
+*
+READ	lda	#$01		1=READ the sector
+	tstb			Make sure 3rd byte of LSN is 0
+	bne	ERROR
+	pshs	x,y		Save these registers for later
+	tst	,s		Check high bit of X (Low 16 bits of LSN)
+	bmi	ERROR2		Should equal 0
+	bsr	GetSect		Go read the sector
+	puls	x,y
+	tfr	x,d
+	tstb			Test one byte of saved X
+	bne	TERM
+	tsta			Test other byte of saved X
+	bne	TERM
+* LSN0, standard OS-9 format
+	ldy	PD.BUF,y	address of buffer
+	leau	DRVBEG,u	point to the beginning of the drive tables
+	ldb	#DD.SIZ		copy bytes over
+copy.0	lda	,y+		grab from LSN0
+	sta	,u+		save into device static storage
+	decb			Finished when B=0
+	bne	copy.0
+	bra	TERM		Return
+
+*
+* Entry:
+*	B = MSB of LSN
+*	X = LSB of LSN
+*	Y = address of path descriptor
+*	U = address of device memory area
+*
+* Exit:
+*	CC = carry set on error
+*	B = error code
+*
+GetSect
+*	orcc	#IntMasks	Kill interrupts
+	pshs	x		save 2 byte LSN
+	ldx	V.PORT,u	get address of hardware
+	sta	RAMDCON,x	Setup for a READ
+	puls	d		Get 2 byte LSN
+	std	RAMDADD,x	Put it in the address
+	ldy	PD.BUF,y	address of buffer 
+	lda	#$80		128 2 byte transfers
+	pshs	a		On stack
+	lda	RAMDDAT+1,x	Start transfer
+LP0	tst	RAMDSTA,x	Is transfer completed?
+	bpl	LP0
+	ldd	RAMDDAT,x	Yes, read 2 bytes from RAM
+	std	,y++		Store them in buffer
+	dec	,s		Are we finished?
+	bne	LP0		No
+	puls	b		clear b
+*	andcc	#^(IntMasks)	Renable Interrupts
+	rts
+
+ERROR2	puls	x,y
+ERROR	ldb	E$SeekRg	Only error is Seek out of Range
+	comb			Set carry bit
+	rts
+
+* Init
+*
+* Entry:
+*	Y = address of device descriptor
+*	U = address of device memory area
+*
+* Exit:
+*	CC = carry set on error
+*	B = error code
+*	
+INIT
+	leax	DRVBEG,u	point to the beginning of the drive tables
+	ldd	#$8000		Number of total sectors
+	stb	DD.TOT,x	$00
+	std	DD.TOT+1,x	$8000
+	ldd	#$0100		A=$01 B=$00
+	stb	V.NDRV,u	$01
+*	lda	#$FF		Probably not needed
+*	sta	V.TRAK,u
+	
+TERM
+* no SetSta calls - return, no error, ignore
+SETSTA
+* no GetSta calls - return, no error, ignore
+GETSTA
+	andcc #^Carry		clear carry
+	 rts
+
+*
+* Entry:
+*	B = MSB of LSN
+*	X = LSB of LSN
+*	Y = address of path descriptor
+*	U = address of device memory area
+*
+* Exit:
+*	CC = carry set on error
+*	B = error code
+*
+WRITE	clra			0 =WRITE to disk
+	tstb			Make sure 3rd byte of LSN is 0
+	bne			ERROR
+	pshs	x,y		Save these registers for later
+	tst	,s		Check high bit of X (Low 16 bits of LSN)
+	bmi	ERROR2		Should equal 0
+* Get Sector comes here with:
+* Entry: A = read/write command code (0/1)
+*	B = MSB of the disk's LSN
+*	X = LSW of the disk's LSN
+*	Y = path dsc. ptr
+*	U = Device static storage ptr
+* Exit:	CC = carry set on error
+*	A = error status from command register
+PutSect
+*	orcc	#IntMasks	Kill interrupts
+	ldx	V.PORT,u	get address of hardware
+	sta	RAMDCON,x	Setup for a READ
+	ldy	PD.BUF,y	address of buffer
+	puls	d		Get 2 byte LSN
+	std	RAMDADD,x	Put it in the address
+	lda	#$80		128 2 byte transfers
+	pshs	a		On stack
+LP2	ldd	,y++		get 2 bytes
+	std	RAMDDAT,x	write them to th RAM
+LP1	tst	RAMDSTA,x	is the transfer completed?
+	bpl	LP1
+	dec	,s
+	bne	LP2
+	puls	b		clear b
+	puls	y
+*	andcc	#^(IntMasks)	Renable Interrupts
+	bra	TERM
+
+	emod
+
+eom	equ	*
\ No newline at end of file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/level2/modules/ramddesc_coco3fpga.asm	Mon Feb 06 22:25:15 2017 +0100
@@ -0,0 +1,84 @@
+********************************************************************
+* ramddesc - SDRAM Disk Device Descriptor Template
+*
+* $Id$
+*
+* Edt/Rev  YYYY/MM/DD  Modified by
+* Comment
+* ------------------------------------------------------------------
+*   1      2016/12/09  Gary Becker
+* Ramdisk driver for the Coco3FPGA DRAM
+*
+
+         nam   ramddesc
+         ttl   RAMD Device Descriptor Template
+
+* Disassembled 98/08/23 17:09:41 by Disasm v1.6 (C) 1988 by RML
+
+*         ifp1  
+          use   defsfile
+*         endc  
+
+tylg     set   Devic+Objct
+atrv     set   ReEnt+rev
+rev      set   $00
+
+	IFNDEF	DNum
+DNum     set   0
+	ENDC
+Type     set   TYP.HARD
+	IFNDEF	Density
+Density  set   DNS.MFM
+	ENDC
+Step     set   STP.6ms
+	IFNDEF	Cyls
+Cyls     set   256
+	ENDC
+	IFNDEF	Cyls_Hi
+Cyls_Hi  set   1
+	ENDC
+Verify   set   1
+	IFNDEF	SectTrk
+SectTrk  set   128
+	ENDC
+	IFNDEF	SectTrk0
+SectTrk0 set   128
+	ENDC
+	IFNDEF	Interlv
+Interlv  set   1
+	ENDC
+	IFNDEF	SAS
+SAS      set   $10
+	ENDC
+
+         mod   eom,name,tylg,atrv,mgrnam,drvnam
+
+         fcb   DIR.!SHARE.!PEXEC.!PWRIT.!PREAD.!EXEC.!UPDAT. mode byte
+         fcb   HW.Page    extended controller address
+         fdb   $FF84      physical controller address
+         fcb   initsize-*-1 initalization table size
+         fcb   DT.RBF     device type:0=scf,1=rbf,2=pipe,3=scf
+         fcb   DNum       drive number
+         fcb   Step       step rate
+         fcb   Type       drive device type
+         fcb   Density    media density:0=single,1=double
+         fdb   Cyls       low number of cylinders (tracks)
+         fcb   Cyls_Hi    high number of cylinders (tracks)
+         fcb   Verify     verify disk writes:0=on
+         fdb   SectTrk    # of sectors per track
+         fdb   SectTrk0   # of sectors per track (track 0)
+         fcb   Interlv    sector interleave factor
+         fcb   SAS        minimum size of sector allocation
+initsize equ   *
+
+         IFNE  DD
+name     fcs   /DD/
+         ELSE
+name     fcb   'R,'0+DNum+$80
+         ENDC
+mgrnam   fcs   /RBF/
+drvnam   fcs   /ramd/
+
+         emod
+eom      equ   *
+         end