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changeset 1891:5f8822fb42e0

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shortened H6309L2 code to fit within $1D0 bytes
author robert
date Fri, 14 Oct 2005 01:53:05 +0000
parents 1021c2fd0c67
children 77d83b367eba
files level1/modules/boot_1773.asm
diffstat 1 files changed, 28 insertions(+), 24 deletions(-) [+]
line wrap: on
line diff
--- a/level1/modules/boot_1773.asm	Wed Oct 12 01:09:22 2005 +0000
+++ b/level1/modules/boot_1773.asm	Fri Oct 14 01:53:05 2005 +0000
@@ -25,6 +25,9 @@
 *
 *   7      2005/10/10  Boisy G. Pitre
 * Added fragmented bootfile support
+*   7      2005/10/13  Robert Gault
+* Changed timing loops for H6309L2 so that code shortened enough to
+* fit within the $1D0 boundary.
 
          nam   Boot
          ttl   WD1773 Boot module
@@ -124,22 +127,26 @@
          sta   CONTROL,y
 * MOTOR ON spin-up delay loop (~307 mSec)
          IFGT  Level-1
-         ldd   #50000
+         IFNE  H6309
+         ldd   #$F000        3 cycles
          ELSE
-         ldd   #25000
-         ENDC
-         IFNE  H6309
-         nop
+         ldd   #50000
+         ENDC 
+         ELSE
+         ldd   #25000 
          ENDC
-L003A    nop
-         nop
-         IFNE  H6309
-         nop
-         nop
-         nop
-         ENDC
-         subd  #$0001
-         bne   L003A
+*         IFNE  H6309
+*         nop
+*         ENDC
+L003A    nop             1 cycles
+         nop             1 cycles
+*         IFNE  H6309
+*         nop
+*         nop
+*         nop
+*         ENDC
+         subd  #$0001    4 cycles
+         bne   L003A     3 cycles
 ************ END OF DEVICE-SPECIFIC INIT ***********
                          
 * Request memory for LSN0
@@ -422,21 +429,18 @@
 DoCMD    bsr   SelNSend
 * Delay branches
 * 54 clock delay including bsr (=30uS/L2,60us/L1)
+* H6309 code changed to reduce code size, RG
+         IFEQ  H6309
 Delay2  
-         IFNE  H6309
-         nop
-         nop
-         ENDC
          lbsr  Delay3
 Delay3 
-         IFNE  H6309
-         nop
-         nop
-         ENDC
          lbsr  Delay4
 Delay4 
-         IFNE  H6309
-         nop
+         ELSE
+Delay2   lda   #5       3 cycles
+Delay3   exg   a,a      5 cycles  | 10*5
+         deca           2 cycles  |
+         bne   Delay3   3 cycles  |
          ENDC
          rts