Mercurial > hg > Members > kono > nitros9-code
changeset 3033:7028ce216ccf
Added SDC boot module from Darren Atkinson
| author | tlindner |
|---|---|
| date | Tue, 23 Dec 2014 21:14:58 -0800 |
| parents | 3afecdae6f53 |
| children | f818de1b815a |
| files | level1/modules/boot_sdc.asm level2/coco3/bootfiles/makefile level2/coco3/makefile level2/coco3/modules/makefile |
| diffstat | 4 files changed, 183 insertions(+), 6 deletions(-) [+] |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/level1/modules/boot_sdc.asm Tue Dec 23 21:14:58 2014 -0800 @@ -0,0 +1,167 @@ +******************************************************************** +* Boot - CoCo SDC Boot module +* +* $Id$ +* +* Edt/Rev YYYY/MM/DD Modified by +* Comment +* ------------------------------------------------------------------ +* 2014/12/22 Darren Atkinson +* Created. + + nam Boot + ttl SDC Boot module + + IFP1 + use defsfile + ENDC + +* Default Boot is from drive 0 +BootDr set 0 + +* Alternate Boot is from drive 1 + IFEQ DNum-1 +BootDr set 1 + ENDC + +* Common booter-required defines +LSN24BIT equ 1 +FLOPPY equ 0 + +* DPort offsets +CONTROL equ 0 write-only +CMDREG equ 8+0 write-only +STATREG equ CMDREG read-only +LSNREG equ 8+1 +DATAREG equ 8+2 + +* NOTE: these are U-stack offsets, not DP +seglist rmb 2 pointer to segment list +blockloc rmb 2 pointer to memory requested +blockimg rmb 2 duplicate of the above +bootsize rmb 2 size in bytes +LSN0Ptr rmb 2 In memory LSN0 pointer +size equ . + + +tylg set Systm+Objct +atrv set ReEnt+rev +rev set $00 +edition set 1 + + mod eom,name,tylg,atrv,start,size + +name fcs /Boot/ + fcb edition + + +*-------------------------------------------------------------------------- +* HWInit - Initialize the device +* +* Entry: +* Y = hardware address +* +* Exit: +* Carry Clear = OK, Set = Error +* B = error (Carry Set) +* +HWInit orcc #$50 mask interrupts + lda #$D0 stop any emulated FDC command + sta CMDREG,y + pshs d,x,y,u delay + puls d,x,y,u + lda STATREG,y clear INTRQ + + *** Fall Thru *** + +*-------------------------------------------------------------------------- +* HWTerm - Terminate the device +* +* Entry: +* Y = hardware address +* +* Exit: +* Carry Clear = OK, Set = Error +* B = error (Carry Set) +* +HWTerm clrb no error + stb CONTROL,y disable command mode + rts + + +*************************************************************************** + use boot_common.asm +*************************************************************************** + +* +* HWRead - Read a 256 byte sector from the device +* +* Entry: +* Y = hardware address +* B = bits 23-16 of LSN +* X = bits 15-0 of LSN +* blockloc,u = where to load the 256 byte sector +* +* Exit: +* X = ptr to data (i.e. ptr in blockloc,u) +* +HWRead lda #$43 start command mode + sta CONTROL,y + stb LSNREG,y put LSN into registers + stx LSNREG+1,y + clra A=0 for use at rdExit + bsr waitSDC wait for BUSY to be cleared + bcs rdExit exit on error or timeout + ldb WhichDrv,pcr get drive number + andb #1 limit to 0 or 1 + orb #$80 combine with Read Sector command + stb CMDREG,y send command to controller + bsr waitSDC wait for data READY + bcs rdExit exit on error or timeout + ldx blockloc,u get address of buffer to fill + pshs u,x preserve U and X + ldb #256/2 1/2 sector size +rdLoop ldu DATAREG,y read word data from controller + stu ,x++ store to buffer + decb decrement word counter + bne rdLoop loop until done + puls x,u restore X and U +rdExit sta CONTROL,y end command mode + rts + + +*-------------------------------------------------------------------------- +* Wait for controller status to indicate either "Not Busy" or "Ready". +* Will time out if neither condition satisfied within a suitable period. +* +* Exit: +* CC.C set on error or time out +* +waitSDC ldx #0 setup timeout counter +waitLp bsr waitRet extra cycles for timeout + comb set carry for timeout/FAILED + leax ,-x decrement timeout counter + beq waitRet return if timed out + ldb STATREG,y read status + bmi waitRet return if FAILED + lsrb BUSY --> Carry + bcc waitRet return if not busy + rolb clear carry + bitb #2 test READY + beq waitLp loop if not ready for transfer +waitRet rts return + + +*-------------------------------------------------------------------------- + + IFGT Level-1 +* Filler to get $1D0 +Filler fill $39,$1D0-3-2-1-* + ENDC + +Address fdb DPort +WhichDrv fcb BootDr + + emod +eom equ * + end
--- a/level2/coco3/bootfiles/makefile Mon Dec 22 21:06:37 2014 -0800 +++ b/level2/coco3/bootfiles/makefile Tue Dec 23 21:14:58 2014 -0800 @@ -10,6 +10,7 @@ KERNEL_DW = $(MD)/rel_80 $(MD)/boot_dw $(MD)/krn KERNEL_ARDUINO = $(MD)/rel_80 $(MD)/boot_dw_arduino $(MD)/krn KERNEL_BECKER = $(MD)/rel_80 $(MD)/boot_dw_becker $(MD)/krn +KERNEL_COCOSDC = $(MD)/rel_80 $(MD)/boot_sdc $(MD)/krn FLOPPY_40D = $(MD)/rb1773.dr $(MD)/d0_40d.dd $(MD)/d1_40d.dd $(MD)/d2_40d.dd FLOPPY_80D = $(MD)/rb1773.dr $(MD)/d0_80d.dd $(MD)/d1_80d.dd $(MD)/d2_80d.dd @@ -159,9 +160,9 @@ # NitrOS-9 disk bootfile to allow booting from CoCo SD BOOTFILE_COCOSDC = $(MD)/krnp2 $(MD)/ioman $(MD)/init \ $(MD)/rbf.mn \ - $(FLOPPY_40D) \ $(RBCOCOSDC) \ - $(MD)/ddsd0_cocosdc.dd \ + $(MD)/ddsd0_cocosdc.dd \ + $(FLOPPY_40D) \ $(MD)/scf.mn \ $(VTIO_COGRF_80) \ $(PIPE) \ @@ -208,7 +209,8 @@ bootfile_80d_50hz bootfile_dw bootfile_dw_headless \ bootfile_becker bootfile_arduino bootfile_becker_headless \ bootfile_arduino_headless bootfile_cocosdc -KERNELS = kernel_1773 kernel_1773_50hz kernel_dw kernel_becker kernel_arduino +KERNELS = kernel_1773 kernel_1773_50hz kernel_dw kernel_becker \ + kernel_arduino kernel_cocosdc ALLOBJS = $(BOOTFILES) $(KERNELS) @@ -264,6 +266,9 @@ kernel_dw: $(KERNEL_DW) $(DEPENDS) $(MERGE) $(KERNEL_DW)>$@ +kernel_cocosdc: $(KERNEL_COCOSDC) $(DEPENDS) + $(MERGE) $(KERNEL_COCOSDC)>$@ + clean: $(RM) $(ALLOBJS)
--- a/level2/coco3/makefile Mon Dec 22 21:06:37 2014 -0800 +++ b/level2/coco3/makefile Tue Dec 23 21:14:58 2014 -0800 @@ -23,6 +23,7 @@ BOOTFILE_80D_50HZ = bootfiles/bootfile_80d_50hz KERNELFILE_BECKER = bootfiles/kernel_becker KERNELFILE_ARDUINO = bootfiles/kernel_arduino +KERNELFILE_COCOSDC = bootfiles/kernel_cocosdc KERNELFILE = bootfiles/kernel_1773 KERNELFILE_50HZ = bootfiles/kernel_1773_50hz KERNELFILE_DW = bootfiles/kernel_dw @@ -223,7 +224,7 @@ $(DSKCOCOSDC): $(RM) $@ $(OS9FORMAT) -t1024 -q $@ -n"NitrOS-9/$(CPU) Level 2" - $(OS9GEN) $@ -b=$(BOOTFILE_COCOSDC) -t=$(KERNELFILE) + $(OS9GEN) $@ -b=$(BOOTFILE_COCOSDC) -t=$(KERNELFILE_COCOSDC) $(MAKDIR) $@,CMDS $(MAKDIR) $@,SYS $(MAKDIR) $@,DEFS
--- a/level2/coco3/modules/makefile Mon Dec 22 21:06:37 2014 -0800 +++ b/level2/coco3/modules/makefile Tue Dec 23 21:14:58 2014 -0800 @@ -24,7 +24,7 @@ BOOTERS = boot_1773_6ms boot_1773_30ms \ boot_burke boot_rampak boot_wd1002 boot_dw boot_dw_becker boot_dw_arduino \ - boot_tc3 boot_ide boot_rom + boot_tc3 boot_ide boot_sdc boot_rom BOOTTRACK = rel_32 rel_40 rel_80 rel_32_50hz rel_40_50hz rel_80_50hz $(BOOTERS) krn KERNEL = krnp2 krnp3_perr krnp4_regdump ccbkrn SYSMODS = ioman init sysgo_h0 sysgo_dd sysgo_rom rominfo vectors @@ -105,6 +105,10 @@ boot_ide: boot_ide.asm $(AS) $(ASOUT)$@ $< $(IDEFLAGS) +# CoCo SDC Booter +boot_sdc: boot_sdc.asm + $(AS) $(ASOUT)$@ $< $(SDFLAGS) + # DriveWire Becker Booter boot_dw_becker: boot_dw.asm $(AS) $< $(ASOUT)$@ $(AFLAGS) -DBECKER=1 @@ -387,7 +391,7 @@ ih_ide.dd: superdesc.asm $(AS) $(ASOUT)$@ $< $(IDEFLAGS) $(HDBDOS) -# SuperSD Descriptors +# CoCo SDC Descriptors ddsd0_cocosdc.dd: superdesc.asm $(AS) $(ASOUT)$@ $< $(SDFLAGS) -DDD=1