Mercurial > hg > Members > kono > nitros9-code
changeset 2711:a1e65a5ef4cf lwtools-port
Moved Atari SIO read/write routines into main dwread.asm and dwwrite.asm
| author | Boisy Pitre <boisy.pitre@nuance.com> |
|---|---|
| date | Tue, 24 Jul 2012 10:09:58 -0500 |
| parents | ab3a2531c000 |
| children | 918dc38f231b |
| files | level1/modules/dwread.asm level1/modules/dwwrite.asm |
| diffstat | 2 files changed, 115 insertions(+), 0 deletions(-) [+] |
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--- a/level1/modules/dwread.asm Tue Jul 24 10:00:38 2012 -0500 +++ b/level1/modules/dwread.asm Tue Jul 24 10:09:58 2012 -0500 @@ -18,7 +18,63 @@ * + IFNE atari +* ATARI SIO Version +DWRead + clrb clear carry + pshs cc,a,x,y,u + tfr x,u + ldx #$0000 + orcc #$50 +* lda D.IRQENSHDW +* sta IRQEN +* ora #%00100000 +* enable the serial input interrupt + + ldb SERIN read what is in the buffer + lda #$13 + sta SKCTL + sta SKRES + +inloop@ + lda D.IRQENSHDW + ora #%00100000 + sta IRQEN + ldd #$0000 +loop@ + subd #$0001 + beq outtahere@ + pshs b + ldb IRQST + bitb #%00100000 + puls b + bne loop@ + ldb SERIN + lda D.IRQENSHDW + sta IRQEN +* check for framing error + lda SKSTAT + bpl outtahere@ framing error + lsla + bpl outtahere@ data input overrun + stb ,u+ + abx + leay -1,y + bne inloop@ + stx 4,s +bye + sta SKRES clear framing or data input overrun bits + puls cc,a,x,y,u,pc +outtahere@ + sta SKRES clear framing or data input overrun bits + puls cc,a + stx 2,s + orcc #$01 + puls x,y,u,pc + + ELSE IFNE BECKER + * NOTE: There is no timeout currently on here... DWRead pshs cc,d,x,u leau ,x @@ -263,3 +319,4 @@ ENDC ENDC ENDC + ENDC \ No newline at end of file
--- a/level1/modules/dwwrite.asm Tue Jul 24 10:00:38 2012 -0500 +++ b/level1/modules/dwwrite.asm Tue Jul 24 10:09:58 2012 -0500 @@ -15,8 +15,65 @@ * All others preserved * + IFNE atari +* Atari SIO Version +* Based on the hipatch source for the Atari and translated +* into 6809 assembly language by Boisy G. Pitre. +* +RMSEND equ %11101111 +SKSEND equ %00100011 +MSKSEND equ %00010000 +IMSEND equ %00010000 +IMSCPL equ $08 +DWWrite + andcc #^$01 ; clear carry to assume no error + pshs d,cc +; setup pokey + lda #$28 + sta AUDCTL +* lda #$A0 + lda #$A8 + sta AUDC4 +* short delay before send + clra +shortdelay@ + deca + bne shortdelay@ + orcc #$50 ; mask interrupts + lda #SKSEND ; set pokey to transmit data mode + sta SKCTL + sta SKRES + lda D.IRQENSHDW + ora #MSKSEND + sta IRQEN + lda ,x+ + sta SEROUT + leay -1,y + beq ex@ +byteloop@ + lda ,x+ + ldb #IMSEND +* NOTE: Potential infinite loop here! +waitloop@ + bitb IRQST + bne waitloop@ + ldb #RMSEND + stb IRQEN + ldb D.IRQENSHDW + orb #MSKSEND + stb IRQEN + sta SEROUT + leay -1,y + bne byteloop@ +ex@ + lda #IMSCPL +wt bita IRQST ; wait until transmit complete + bne wt + puls cc,d,pc + ELSE IFNE BECKER + DWWrite pshs d,cc ; preserve registers orcc #$50 ; mask interrupts ; ldu #BBOUT ; point U to bit banger out register @@ -191,3 +248,4 @@ ENDC ENDC ENDC + ENDC