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changeset 3175:b67b40d76fb0

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Adding Co42 to coco makefiles
author lfantoniosi
date Sun, 14 May 2017 10:16:09 -0700
parents 5fad6ee804ba
children 8bffec52cae5
files level1/coco1/bootfiles/makefile level1/coco1/makefile level1/coco1/modules/makefile
diffstat 3 files changed, 74 insertions(+), 6 deletions(-) [+]
line wrap: on
line diff
--- a/level1/coco1/bootfiles/makefile	Sun May 14 00:15:38 2017 -0700
+++ b/level1/coco1/bootfiles/makefile	Sun May 14 10:16:09 2017 -0700
@@ -37,6 +37,7 @@
 VTIO_COVDG	= $(MD)/vtio.dr $(MD)/covdg.io $(MD)/term_vdg.dt
 VTIO_COHR	= $(MD)/vtio.dr $(MD)/cohr.io $(MD)/term_hr.dt
 VTIO_CO80	= $(MD)/vtio.dr $(MD)/co80.io $(MD)/term_80.dt
+VTIO_CO42	= $(MD)/vtio.dr $(MD)/co42.io $(MD)/term_42.dt
 PIPE		= $(MD)/pipeman.mn $(MD)/piper.dr $(MD)/pipe.dd
 CLOCK60HZ	= $(MD)/clock_60hz $(MD)/clock2_soft
 CLOCK60HZDW	= $(MD)/clock_60hz $(MD)/clock2_dw
@@ -90,6 +91,18 @@
 		$(CLOCK60HZ) \
 		$(MD)/sysgo_dd
 
+BOOTFILE_CO42	= $(MD)/ioman \
+		$(MD)/rbf.mn \
+		$(FLOPPY_40D) \
+		$(MD)/ddd0_40d.dd \
+		$(MD)/scf.mn \
+		$(VTIO_CO42) \
+		$(MD)/scbbp.dr $(MD)/p_scbbp.dd \
+		$(MD)/scbbt.dr $(MD)/t1_scbbt.dd \
+		$(PIPE) \
+		$(CLOCK60HZ) \
+		$(MD)/sysgo_dd
+
 BOOTFILE_CO80	= $(MD)/ioman \
 		$(MD)/rbf.mn \
 		$(FLOPPY_40D) \
@@ -244,6 +257,19 @@
 		$(CLOCK60HZ) \
 		$(MD)/sysgo_dd
 
+BOOTFILE_CO42_COCOSDC	= $(MD)/ioman \
+		$(MD)/rbf.mn \
+		$(RBCOCOSDC) \
+		$(MD)/ddsd0_cocosdc.dd \
+		$(FLOPPY_40D) \
+		$(MD)/scf.mn \
+		$(VTIO_CO42) \
+		$(MD)/scbbp.dr $(MD)/p_scbbp.dd \
+		$(MD)/scbbt.dr $(MD)/t1_scbbt.dd \
+		$(PIPE) \
+		$(CLOCK60HZ) \
+		$(MD)/sysgo_dd		
+
 BOOTFILE_COVDG_COCOSDC_GAME	= $(MD)/ioman \
 		$(MD)/rbf.mn \
 		$(RBCOCOSDC) \
@@ -269,6 +295,20 @@
 		$(CLOCK60HZDW) \
 		$(MD)/sysgo_dd
 
+BOOTFILE_CO42_DW	= $(MD)/ioman \
+		$(MD)/rbf.mn \
+		$(FLOPPY_40D) \
+		$(RBDW) \
+		$(MD)/ddx0.dd \
+		$(MD)/scf.mn \
+		$(VTIO_CO42) \
+		$(MD)/scdwv.dr \
+		$(SCDWV_NET) \
+		$(SCDWP)\
+		$(PIPE) \
+		$(CLOCK60HZDW) \
+		$(MD)/sysgo_dd
+
 BOOTFILE_COHR_BECKER	= $(MD)/ioman \
 		$(MD)/rbf.mn \
 		$(FLOPPY_40D) \
@@ -302,18 +342,31 @@
 		$(FLOPPY_80D) \
 		$(MD)/ddd0_80d.dd \
 		$(MD)/scf.mn \
-		$(VTIO_CO80) \
+		$(VTIO_COHR) \
 		$(MD)/scbbp.dr $(MD)/p_scbbp.dd \
 		$(MD)/scbbt.dr $(MD)/t1_scbbt.dd \
 		$(PIPE) \
 		$(CLOCK60HZ) \
 		$(MD)/sysgo_dd
 
-BOOTFILES	= bootfile_covdg bootfile_cohr bootfile_covdg_dw \
+BOOTFILE_CO42_DS80	= $(MD)/ioman \
+		$(MD)/rbf.mn \
+		$(FLOPPY_80D) \
+		$(MD)/ddd0_80d.dd \
+		$(MD)/scf.mn \
+		$(VTIO_CO42) \
+		$(MD)/scbbp.dr $(MD)/p_scbbp.dd \
+		$(MD)/scbbt.dr $(MD)/t1_scbbt.dd \
+		$(PIPE) \
+		$(CLOCK60HZ) \
+		$(MD)/sysgo_dd
+
+BOOTFILES	= bootfile_covdg bootfile_cohr bootfile_co42  \
 		bootfile_dw_headless bootfile_covdg_becker \
 		bootfile_covdg_becker_game bootfile_covdg_dw_game \
-		bootfile_covdg_cocosdc bootfile_covdg_cocosdc_game \
-		bootfile_cohr_dw bootfile_covdg_ds80 bootfile_cohr_ds80 \
+		bootfile_covdg_cocosdc bootfile_co42_cocosdc bootfile_covdg_cocosdc_game \
+		bootfile_covdg_dw bootfile_cohr_dw bootfile_co42_dw \
+		bootfile_covdg_ds80 bootfile_cohr_ds80 bootfile_co42_ds80 \
 		bootfile_cohr_becker bootfile_becker_headless \
 		bootfile_covdg_arduino bootfile_arduino_headless \
 		bootfile_cohr_arduino bootfile_covdg_arduino_game 
@@ -330,6 +383,9 @@
 bootfile_cohr: $(BOOTFILE_COHR) $(DEPENDS)
 	$(MERGE) $(BOOTFILE_COHR)>$@
 
+bootfile_co42: $(BOOTFILE_CO42) $(DEPENDS)
+	$(MERGE) $(BOOTFILE_CO42)>$@
+
 bootfile_co80: $(BOOTFILE_CO80) $(DEPENDS)
 	$(MERGE) $(BOOTFILE_CO80)>$@
 
@@ -366,15 +422,24 @@
 bootfile_covdg_cocosdc: $(BOOTFILE_COVDG_COCOSDC) $(DEPENDS)
 	$(MERGE) $(BOOTFILE_COVDG_COCOSDC)>$@
 
+bootfile_co42_cocosdc: $(BOOTFILE_CO42_COCOSDC) $(DEPENDS)
+	$(MERGE) $(BOOTFILE_CO42_COCOSDC)>$@
+
 bootfile_covdg_cocosdc_game: $(BOOTFILE_COVDG_COCOSDC_GAME) $(DEPENDS)
 	$(MERGE) $(BOOTFILE_COVDG_COCOSDC_GAME)>$@
 
 bootfile_cohr_ds80: $(BOOTFILE_COHR_DS80) $(DEPENDS)
 	$(MERGE) $(BOOTFILE_COHR_DS80)>$@
 
+bootfile_co42_ds80: $(BOOTFILE_CO42_DS80) $(DEPENDS)
+	$(MERGE) $(BOOTFILE_CO42_DS80)>$@
+
 bootfile_cohr_dw: $(BOOTFILE_COHR_DW) $(DEPENDS)
 	$(MERGE) $(BOOTFILE_COHR_DW)>$@
 
+bootfile_co42_dw: $(BOOTFILE_CO42_DW) $(DEPENDS)
+	$(MERGE) $(BOOTFILE_CO42_DW)>$@
+
 bootfile_cohr_becker: $(BOOTFILE_COHR_BECKER) $(DEPENDS)
 	$(MERGE) $(BOOTFILE_COHR_BECKER)>$@
 
--- a/level1/coco1/makefile	Sun May 14 00:15:38 2017 -0700
+++ b/level1/coco1/makefile	Sun May 14 10:16:09 2017 -0700
@@ -9,6 +9,7 @@
 DISTROVER	= $(DISTRONAME)$(NITROS9VER)$(PORT)
 BOOTFILE_COVDG	= bootfiles/bootfile_covdg
 BOOTFILE_COHR	= bootfiles/bootfile_cohr
+BOOTFILE_CO42	= bootfiles/bootfile_co42
 BOOTFILE_COVDG_DS80	= bootfiles/bootfile_covdg_ds80
 BOOTFILE_DW_HEADLESS	= bootfiles/bootfile_dw_headless
 BOOTFILE_BECKER_HEADLESS	= bootfiles/bootfile_becker_headless
@@ -18,7 +19,9 @@
 BOOTFILE_COVDG_ARDUINO	= bootfiles/bootfile_covdg_arduino
 BOOTFILE_COVDG_COCOSDC	= bootfiles/bootfile_covdg_cocosdc
 BOOTFILE_COHR_DS80	= bootfiles/bootfile_cohr_ds80
+BOOTFILE_CO42_DS80	= bootfiles/bootfile_co42_ds80
 BOOTFILE_COHR_DW	= bootfiles/bootfile_cohr_dw
+BOOTFILE_CO42_DW	= bootfiles/bootfile_co42_dw
 BOOTFILE_COHR_BECKER	= bootfiles/bootfile_cohr_becker
 BOOTFILE_COHR_ARDUINO	= bootfiles/bootfile_cohr_arduino
 KERNELFILE	= bootfiles/kernel_1773
--- a/level1/coco1/modules/makefile	Sun May 14 00:15:38 2017 -0700
+++ b/level1/coco1/modules/makefile	Sun May 14 10:16:09 2017 -0700
@@ -48,10 +48,10 @@
 
 SCF		= scf.mn \
 		sc6551.dr vrn.dr scbbp.dr scbbt.dr scdwp.dr sspak.dr vtio.dr \
-		covdg.io cohr.io co80.io \
+		covdg.io cohr.io co42.io co80.io \
 		nil.dd p_scbbp.dd p_scdwp.dd pipe.dd ssp.dd \
 		term_scbbt.dt term_sc6551.dt t1_scbbt.dd t2_sc6551.dd t3_sc6551.dd \
-		term_vdg.dt term_hr.dt term_80.dt \
+		term_vdg.dt term_hr.dt term_42.dt term_80.dt \
 		scdwv.dr term_scdwv.dt n_scdwv.dd n1_scdwv.dd n2_scdwv.dd \
 		n3_scdwv.dd n4_scdwv.dd n5_scdwv.dd n6_scdwv.dd n7_scdwv.dd \
 		n8_scdwv.dd n9_scdwv.dd n10_scdwv.dd n11_scdwv.dd n12_scdwv.dd \