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comparison engine.c @ 4:6159cc57d44e

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author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 04 Jul 2018 19:33:22 +0900
parents 9a224bd9b45f
children 35028b396a35
comparison
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3:831ac057ea86 4:6159cc57d44e
37 Byte aca,acb; 37 Byte aca,acb;
38 Byte *breg=&aca,*areg=&acb; 38 Byte *breg=&aca,*areg=&acb;
39 static int tracetrick=0; 39 static int tracetrick=0;
40 extern int romstart; 40 extern int romstart;
41 41
42 #define GETWORD(a) (mem[a]<<8|mem[(a)+1]) 42 #ifdef USE_MMU
43 #define SETBYTE(a,n) {if(!(a>=romstart))mem[a]=n;} 43 inline Byte * mem0(Word adr, Byte *immu) { return & iphymem[ ( immu[ (adr) >> 13 ] <<13 ) + ((adr) & 0x1fff )] }
44 #define SETWORD(a,n) if(!(a>=romstart)){mem[a]=(n)>>8;mem[(a)+1]=n;} 44 #define mem(adr) mem0(adr,immu)
45 #else
46 #define mem(adr) mem[adr]
47 #endif
48
49
50 #define GETWORD(a) (mem(a)<<8|mem((a)+1))
51 #define SETBYTE(a,n) {if(!(a>=romstart))mem(a)=n;}
52 #define SETWORD(a,n) if(!(a>=romstart)){mem(a)=(n)>>8;mem((a)+1)=n;}
45 /* Two bytes of a word are fetched separately because of 53 /* Two bytes of a word are fetched separately because of
46 the possible wrap-around at address $ffff and alignment 54 the possible wrap-around at address $ffff and alignment
47 */ 55 */
48 56
49 #define IMMBYTE(b) b=mem[ipcreg++]; 57 #define IMMBYTE(b) b=mem(ipcreg++);
50 #define IMMWORD(w) {w=GETWORD(ipcreg);ipcreg+=2;} 58 #define IMMWORD(w) {w=GETWORD(ipcreg);ipcreg+=2;}
51 59
52 #define PUSHBYTE(b) {--isreg;SETBYTE(isreg,b)} 60 #define PUSHBYTE(b) {--isreg;SETBYTE(isreg,b)}
53 #define PUSHWORD(w) {isreg-=2;SETWORD(isreg,w)} 61 #define PUSHWORD(w) {isreg-=2;SETWORD(isreg,w)}
54 #define PULLBYTE(b) b=mem[isreg++]; 62 #define PULLBYTE(b) b=mem(isreg++);
55 #define PULLWORD(w) {w=GETWORD(isreg);isreg+=2;} 63 #define PULLWORD(w) {w=GETWORD(isreg);isreg+=2;}
56 #define PSHUBYTE(b) {--iureg;SETBYTE(iureg,b)} 64 #define PSHUBYTE(b) {--iureg;SETBYTE(iureg,b)}
57 #define PSHUWORD(w) {iureg-=2;SETWORD(iureg,w)} 65 #define PSHUWORD(w) {iureg-=2;SETWORD(iureg,w)}
58 #define PULUBYTE(b) b=mem[iureg++]; 66 #define PULUBYTE(b) b=mem(iureg++);
59 #define PULUWORD(w) {w=GETWORD(iureg);iureg+=2;} 67 #define PULUWORD(w) {w=GETWORD(iureg);iureg+=2;}
60 68
61 #define SIGNED(b) ((Word)(b&0x80?b|0xff00:b)) 69 #define SIGNED(b) ((Word)(b&0x80?b|0xff00:b))
62 70
63 #define GETDREG ((iareg<<8)|ibreg) 71 #define GETDREG ((iareg<<8)|ibreg)
123 case 10: iccreg=val;break;\ 131 case 10: iccreg=val;break;\
124 case 11: idpreg=val;break;} 132 case 11: idpreg=val;break;}
125 133
126 /* Macros for load and store of accumulators. Can be modified to check 134 /* Macros for load and store of accumulators. Can be modified to check
127 for port addresses */ 135 for port addresses */
128 #define LOADAC(reg) if((eaddr&0xff00)!=IOPAGE)reg=mem[eaddr];else\ 136 #define LOADAC(reg) if((eaddr&0xff00)!=IOPAGE)reg=mem(eaddr);else\
129 reg=do_input(eaddr&0xff); 137 reg=do_input(eaddr&0xff);
130 #define STOREAC(reg) if((eaddr&0xff00)!=IOPAGE)SETBYTE(eaddr,reg)else\ 138 #define STOREAC(reg) if((eaddr&0xff00)!=IOPAGE)SETBYTE(eaddr,reg)else\
131 do_output(eaddr&0xff,reg); 139 do_output(eaddr&0xff,reg);
132 140
133 #define LOADREGS ixreg=xreg;iyreg=yreg;\ 141 #define LOADREGS ixreg=xreg;iyreg=yreg;\
134 iureg=ureg;isreg=sreg;\ 142 iureg=ureg;isreg=sreg;\
135 ipcreg=pcreg;\ 143 ipcreg=pcreg;\
136 iareg=*areg;ibreg=*breg;\ 144 iareg=*areg;ibreg=*breg;\
137 idpreg=dpreg;iccreg=ccreg; 145 idpreg=dpreg;iccreg=ccreg;immu=mmu;
138 146
139 #define SAVEREGS xreg=ixreg;yreg=iyreg;\ 147 #define SAVEREGS xreg=ixreg;yreg=iyreg;\
140 ureg=iureg;sreg=isreg;\ 148 ureg=iureg;sreg=isreg;\
141 pcreg=ipcreg;\ 149 pcreg=ipcreg;\
142 *areg=iareg;*breg=ibreg;\ 150 *areg=iareg;*breg=ibreg;\
143 dpreg=idpreg;ccreg=iccreg; 151 dpreg=idpreg;ccreg=iccreg;mmu=immu;
144 152
145 153
146 unsigned char haspostbyte[] = { 154 unsigned char haspostbyte[] = {
147 /*0*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 155 /*0*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
148 /*1*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 156 /*1*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
170 these could be implemented as fast registers. */ 178 these could be implemented as fast registers. */
171 Word eaddr; /* effective address */ 179 Word eaddr; /* effective address */
172 Byte ireg; /* instruction register */ 180 Byte ireg; /* instruction register */
173 Byte iflag; /* flag to indicate $10 or $11 prebyte */ 181 Byte iflag; /* flag to indicate $10 or $11 prebyte */
174 Byte tb;Word tw; 182 Byte tb;Word tw;
183 Byte *immu = 0;
184 #ifdef USE_MMU
185 const int imemsize = memsize;
186 Byte *iphymem = (Byte *)phymem;
187 immu = iphymem + imemsize - 0x10000 + 0xffa0;
188 #endif
175 LOADREGS 189 LOADREGS
176 for(;;){ 190 for(;;){
177 if(attention) { 191 if(attention) {
178 if(tracing && ipcreg>=tracelo && ipcreg<=tracehi) 192 if(tracing && ipcreg>=tracelo && ipcreg<=tracehi)
179 {SAVEREGS do_trace(tracefile); } 193 {SAVEREGS do_trace(tracefile); }
202 irq=0; 216 irq=0;
203 } 217 }
204 } 218 }
205 iflag=0; 219 iflag=0;
206 flaginstr: /* $10 and $11 instructions return here */ 220 flaginstr: /* $10 and $11 instructions return here */
207 ireg=mem[ipcreg++]; 221 ireg=mem(ipcreg++);
208 if(haspostbyte[ireg]) { 222 if(haspostbyte[ireg]) {
209 Byte postbyte=mem[ipcreg++]; 223 Byte postbyte=mem(ipcreg++);
210 switch(postbyte) { 224 switch(postbyte) {
211 case 0x00: eaddr=ixreg;break; 225 case 0x00: eaddr=ixreg;break;
212 case 0x01: eaddr=ixreg+1;break; 226 case 0x01: eaddr=ixreg+1;break;
213 case 0x02: eaddr=ixreg+2;break; 227 case 0x02: eaddr=ixreg+2;break;
214 case 0x03: eaddr=ixreg+3;break; 228 case 0x03: eaddr=ixreg+3;break;
473 case 0xFE: eaddr=0;break; /*ILLEGAL*/ 487 case 0xFE: eaddr=0;break; /*ILLEGAL*/
474 case 0xFF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break; 488 case 0xFF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break;
475 } 489 }
476 } 490 }
477 switch(ireg) { 491 switch(ireg) {
478 case 0x00: /*NEG direct*/ DIRECT tw=-mem[eaddr];SETSTATUS(0,mem[eaddr],tw) 492 case 0x00: /*NEG direct*/ DIRECT tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw)
479 SETBYTE(eaddr,tw)break; 493 SETBYTE(eaddr,tw)break;
480 case 0x01: break;/*ILLEGAL*/ 494 case 0x01: break;/*ILLEGAL*/
481 case 0x02: break;/*ILLEGAL*/ 495 case 0x02: break;/*ILLEGAL*/
482 case 0x03: /*COM direct*/ DIRECT tb=~mem[eaddr];SETNZ8(tb);SEC CLV 496 case 0x03: /*COM direct*/ DIRECT tb=~mem(eaddr);SETNZ8(tb);SEC CLV
483 SETBYTE(eaddr,tb)break; 497 SETBYTE(eaddr,tb)break;
484 case 0x04: /*LSR direct*/ DIRECT tb=mem[eaddr];if(tb&0x01)SEC else CLC 498 case 0x04: /*LSR direct*/ DIRECT tb=mem(eaddr);if(tb&0x01)SEC else CLC
485 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) 499 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
486 SETBYTE(eaddr,tb)break; 500 SETBYTE(eaddr,tb)break;
487 case 0x05: break;/* ILLEGAL*/ 501 case 0x05: break;/* ILLEGAL*/
488 case 0x06: /*ROR direct*/ DIRECT tb=(iccreg&0x01)<<7; 502 case 0x06: /*ROR direct*/ DIRECT tb=(iccreg&0x01)<<7;
489 if(mem[eaddr]&0x01)SEC else CLC 503 if(mem(eaddr)&0x01)SEC else CLC
490 tw=(mem[eaddr]>>1)+tb;SETNZ8(tw) 504 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw)
491 SETBYTE(eaddr,tw) 505 SETBYTE(eaddr,tw)
492 break; 506 break;
493 case 0x07: /*ASR direct*/ DIRECT tb=mem[eaddr];if(tb&0x01)SEC else CLC 507 case 0x07: /*ASR direct*/ DIRECT tb=mem(eaddr);if(tb&0x01)SEC else CLC
494 if(tb&0x10)SEH else CLH tb>>=1; 508 if(tb&0x10)SEH else CLH tb>>=1;
495 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) 509 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb)
496 break; 510 break;
497 case 0x08: /*ASL direct*/ DIRECT tw=mem[eaddr]<<1; 511 case 0x08: /*ASL direct*/ DIRECT tw=mem(eaddr)<<1;
498 SETSTATUS(mem[eaddr],mem[eaddr],tw) 512 SETSTATUS(mem(eaddr),mem(eaddr),tw)
499 SETBYTE(eaddr,tw)break; 513 SETBYTE(eaddr,tw)break;
500 case 0x09: /*ROL direct*/ DIRECT tb=mem[eaddr];tw=iccreg&0x01; 514 case 0x09: /*ROL direct*/ DIRECT tb=mem(eaddr);tw=iccreg&0x01;
501 if(tb&0x80)SEC else CLC 515 if(tb&0x80)SEC else CLC
502 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV 516 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
503 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; 517 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break;
504 case 0x0A: /*DEC direct*/ DIRECT tb=mem[eaddr]-1;if(tb==0x7F)SEV else CLV 518 case 0x0A: /*DEC direct*/ DIRECT tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV
505 SETNZ8(tb) SETBYTE(eaddr,tb)break; 519 SETNZ8(tb) SETBYTE(eaddr,tb)break;
506 case 0x0B: break; /*ILLEGAL*/ 520 case 0x0B: break; /*ILLEGAL*/
507 case 0x0C: /*INC direct*/ DIRECT tb=mem[eaddr]+1;if(tb==0x80)SEV else CLV 521 case 0x0C: /*INC direct*/ DIRECT tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV
508 SETNZ8(tb) SETBYTE(eaddr,tb)break; 522 SETNZ8(tb) SETBYTE(eaddr,tb)break;
509 case 0x0D: /*TST direct*/ DIRECT tb=mem[eaddr];SETNZ8(tb) break; 523 case 0x0D: /*TST direct*/ DIRECT tb=mem(eaddr);SETNZ8(tb) break;
510 case 0x0E: /*JMP direct*/ DIRECT ipcreg=eaddr;break; 524 case 0x0E: /*JMP direct*/ DIRECT ipcreg=eaddr;break;
511 case 0x0F: /*CLR direct*/ DIRECT SETBYTE(eaddr,0);CLN CLV SEZ CLC break; 525 case 0x0F: /*CLR direct*/ DIRECT SETBYTE(eaddr,0);CLN CLV SEZ CLC break;
512 case 0x10: /* flag10 */ iflag=1;goto flaginstr; 526 case 0x10: /* flag10 */ iflag=1;goto flaginstr;
513 case 0x11: /* flag11 */ iflag=2;goto flaginstr; 527 case 0x11: /* flag11 */ iflag=2;goto flaginstr;
514 case 0x12: /* NOP */ break; 528 case 0x12: /* NOP */ break;
716 case 0x5C: /*INCB*/ tb=ibreg+1;if(tb==0x80)SEV else CLV 730 case 0x5C: /*INCB*/ tb=ibreg+1;if(tb==0x80)SEV else CLV
717 SETNZ8(tb) ibreg=tb;break; 731 SETNZ8(tb) ibreg=tb;break;
718 case 0x5D: /*TSTB*/ SETNZ8(ibreg) break; 732 case 0x5D: /*TSTB*/ SETNZ8(ibreg) break;
719 case 0x5E: break; /*ILLEGAL*/ 733 case 0x5E: break; /*ILLEGAL*/
720 case 0x5F: /*CLRB*/ ibreg=0;CLN CLV SEZ CLC break; 734 case 0x5F: /*CLRB*/ ibreg=0;CLN CLV SEZ CLC break;
721 case 0x60: /*NEG indexed*/ tw=-mem[eaddr];SETSTATUS(0,mem[eaddr],tw) 735 case 0x60: /*NEG indexed*/ tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw)
722 SETBYTE(eaddr,tw)break; 736 SETBYTE(eaddr,tw)break;
723 case 0x61: break;/*ILLEGAL*/ 737 case 0x61: break;/*ILLEGAL*/
724 case 0x62: break;/*ILLEGAL*/ 738 case 0x62: break;/*ILLEGAL*/
725 case 0x63: /*COM indexed*/ tb=~mem[eaddr];SETNZ8(tb);SEC CLV 739 case 0x63: /*COM indexed*/ tb=~mem(eaddr);SETNZ8(tb);SEC CLV
726 SETBYTE(eaddr,tb)break; 740 SETBYTE(eaddr,tb)break;
727 case 0x64: /*LSR indexed*/ tb=mem[eaddr];if(tb&0x01)SEC else CLC 741 case 0x64: /*LSR indexed*/ tb=mem(eaddr);if(tb&0x01)SEC else CLC
728 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) 742 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
729 SETBYTE(eaddr,tb)break; 743 SETBYTE(eaddr,tb)break;
730 case 0x65: break;/* ILLEGAL*/ 744 case 0x65: break;/* ILLEGAL*/
731 case 0x66: /*ROR indexed*/ tb=(iccreg&0x01)<<7; 745 case 0x66: /*ROR indexed*/ tb=(iccreg&0x01)<<7;
732 if(mem[eaddr]&0x01)SEC else CLC 746 if(mem(eaddr)&0x01)SEC else CLC
733 tw=(mem[eaddr]>>1)+tb;SETNZ8(tw) 747 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw)
734 SETBYTE(eaddr,tw) 748 SETBYTE(eaddr,tw)
735 break; 749 break;
736 case 0x67: /*ASR indexed*/ tb=mem[eaddr];if(tb&0x01)SEC else CLC 750 case 0x67: /*ASR indexed*/ tb=mem(eaddr);if(tb&0x01)SEC else CLC
737 if(tb&0x10)SEH else CLH tb>>=1; 751 if(tb&0x10)SEH else CLH tb>>=1;
738 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) 752 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb)
739 break; 753 break;
740 case 0x68: /*ASL indexed*/ tw=mem[eaddr]<<1; 754 case 0x68: /*ASL indexed*/ tw=mem(eaddr)<<1;
741 SETSTATUS(mem[eaddr],mem[eaddr],tw) 755 SETSTATUS(mem(eaddr),mem(eaddr),tw)
742 SETBYTE(eaddr,tw)break; 756 SETBYTE(eaddr,tw)break;
743 case 0x69: /*ROL indexed*/ tb=mem[eaddr];tw=iccreg&0x01; 757 case 0x69: /*ROL indexed*/ tb=mem(eaddr);tw=iccreg&0x01;
744 if(tb&0x80)SEC else CLC 758 if(tb&0x80)SEC else CLC
745 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV 759 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
746 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; 760 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break;
747 case 0x6A: /*DEC indexed*/ tb=mem[eaddr]-1;if(tb==0x7F)SEV else CLV 761 case 0x6A: /*DEC indexed*/ tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV
748 SETNZ8(tb) SETBYTE(eaddr,tb)break; 762 SETNZ8(tb) SETBYTE(eaddr,tb)break;
749 case 0x6B: break; /*ILLEGAL*/ 763 case 0x6B: break; /*ILLEGAL*/
750 case 0x6C: /*INC indexed*/ tb=mem[eaddr]+1;if(tb==0x80)SEV else CLV 764 case 0x6C: /*INC indexed*/ tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV
751 SETNZ8(tb) SETBYTE(eaddr,tb)break; 765 SETNZ8(tb) SETBYTE(eaddr,tb)break;
752 case 0x6D: /*TST indexed*/ tb=mem[eaddr];SETNZ8(tb) break; 766 case 0x6D: /*TST indexed*/ tb=mem(eaddr);SETNZ8(tb) break;
753 case 0x6E: /*JMP indexed*/ ipcreg=eaddr;break; 767 case 0x6E: /*JMP indexed*/ ipcreg=eaddr;break;
754 case 0x6F: /*CLR indexed*/ SETBYTE(eaddr,0)CLN CLV SEZ CLC break; 768 case 0x6F: /*CLR indexed*/ SETBYTE(eaddr,0)CLN CLV SEZ CLC break;
755 case 0x70: /*NEG ext*/ EXTENDED tw=-mem[eaddr];SETSTATUS(0,mem[eaddr],tw) 769 case 0x70: /*NEG ext*/ EXTENDED tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw)
756 SETBYTE(eaddr,tw)break; 770 SETBYTE(eaddr,tw)break;
757 case 0x71: break;/*ILLEGAL*/ 771 case 0x71: break;/*ILLEGAL*/
758 case 0x72: break;/*ILLEGAL*/ 772 case 0x72: break;/*ILLEGAL*/
759 case 0x73: /*COM ext*/ EXTENDED tb=~mem[eaddr];SETNZ8(tb);SEC CLV 773 case 0x73: /*COM ext*/ EXTENDED tb=~mem(eaddr);SETNZ8(tb);SEC CLV
760 SETBYTE(eaddr,tb)break; 774 SETBYTE(eaddr,tb)break;
761 case 0x74: /*LSR ext*/ EXTENDED tb=mem[eaddr];if(tb&0x01)SEC else CLC 775 case 0x74: /*LSR ext*/ EXTENDED tb=mem(eaddr);if(tb&0x01)SEC else CLC
762 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb) 776 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
763 SETBYTE(eaddr,tb)break; 777 SETBYTE(eaddr,tb)break;
764 case 0x75: break;/* ILLEGAL*/ 778 case 0x75: break;/* ILLEGAL*/
765 case 0x76: /*ROR ext*/ EXTENDED tb=(iccreg&0x01)<<7; 779 case 0x76: /*ROR ext*/ EXTENDED tb=(iccreg&0x01)<<7;
766 if(mem[eaddr]&0x01)SEC else CLC 780 if(mem(eaddr)&0x01)SEC else CLC
767 tw=(mem[eaddr]>>1)+tb;SETNZ8(tw) 781 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw)
768 SETBYTE(eaddr,tw) 782 SETBYTE(eaddr,tw)
769 break; 783 break;
770 case 0x77: /*ASR ext*/ EXTENDED tb=mem[eaddr];if(tb&0x01)SEC else CLC 784 case 0x77: /*ASR ext*/ EXTENDED tb=mem(eaddr);if(tb&0x01)SEC else CLC
771 if(tb&0x10)SEH else CLH tb>>=1; 785 if(tb&0x10)SEH else CLH tb>>=1;
772 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb) 786 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb)
773 break; 787 break;
774 case 0x78: /*ASL ext*/ EXTENDED tw=mem[eaddr]<<1; 788 case 0x78: /*ASL ext*/ EXTENDED tw=mem(eaddr)<<1;
775 SETSTATUS(mem[eaddr],mem[eaddr],tw) 789 SETSTATUS(mem(eaddr),mem(eaddr),tw)
776 SETBYTE(eaddr,tw)break; 790 SETBYTE(eaddr,tw)break;
777 case 0x79: /*ROL ext*/ EXTENDED tb=mem[eaddr];tw=iccreg&0x01; 791 case 0x79: /*ROL ext*/ EXTENDED tb=mem(eaddr);tw=iccreg&0x01;
778 if(tb&0x80)SEC else CLC 792 if(tb&0x80)SEC else CLC
779 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV 793 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
780 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break; 794 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break;
781 case 0x7A: /*DEC ext*/ EXTENDED tb=mem[eaddr]-1;if(tb==0x7F)SEV else CLV 795 case 0x7A: /*DEC ext*/ EXTENDED tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV
782 SETNZ8(tb) SETBYTE(eaddr,tb)break; 796 SETNZ8(tb) SETBYTE(eaddr,tb)break;
783 case 0x7B: break; /*ILLEGAL*/ 797 case 0x7B: break; /*ILLEGAL*/
784 case 0x7C: /*INC ext*/ EXTENDED tb=mem[eaddr]+1;if(tb==0x80)SEV else CLV 798 case 0x7C: /*INC ext*/ EXTENDED tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV
785 SETNZ8(tb) SETBYTE(eaddr,tb)break; 799 SETNZ8(tb) SETBYTE(eaddr,tb)break;
786 case 0x7D: /*TST ext*/ EXTENDED tb=mem[eaddr];SETNZ8(tb) break; 800 case 0x7D: /*TST ext*/ EXTENDED tb=mem(eaddr);SETNZ8(tb) break;
787 case 0x7E: /*JMP ext*/ EXTENDED ipcreg=eaddr;break; 801 case 0x7E: /*JMP ext*/ EXTENDED ipcreg=eaddr;break;
788 case 0x7F: /*CLR ext*/ EXTENDED SETBYTE(eaddr,0)CLN CLV SEZ CLC break; 802 case 0x7F: /*CLR ext*/ EXTENDED SETBYTE(eaddr,0)CLN CLV SEZ CLC break;
789 case 0x80: /*SUBA immediate*/ IMM8 tw=iareg-mem[eaddr]; 803 case 0x80: /*SUBA immediate*/ IMM8 tw=iareg-mem(eaddr);
790 SETSTATUS(iareg,mem[eaddr],tw) 804 SETSTATUS(iareg,mem(eaddr),tw)
791 iareg=tw;break; 805 iareg=tw;break;
792 case 0x81: /*CMPA immediate*/ IMM8 tw=iareg-mem[eaddr]; 806 case 0x81: /*CMPA immediate*/ IMM8 tw=iareg-mem(eaddr);
793 SETSTATUS(iareg,mem[eaddr],tw) break; 807 SETSTATUS(iareg,mem(eaddr),tw) break;
794 case 0x82: /*SBCA immediate*/ IMM8 tw=iareg-mem[eaddr]-(iccreg&0x01); 808 case 0x82: /*SBCA immediate*/ IMM8 tw=iareg-mem(eaddr)-(iccreg&0x01);
795 SETSTATUS(iareg,mem[eaddr],tw) 809 SETSTATUS(iareg,mem(eaddr),tw)
796 iareg=tw;break; 810 iareg=tw;break;
797 case 0x83: /*SUBD (CMPD CMPU) immediate*/ IMM16 811 case 0x83: /*SUBD (CMPD CMPU) immediate*/ IMM16
798 {unsigned long res,dreg,breg; 812 {unsigned long res,dreg,breg;
799 if(iflag==2)dreg=iureg;else dreg=GETDREG; 813 if(iflag==2)dreg=iureg;else dreg=GETDREG;
800 breg=GETWORD(eaddr); 814 breg=GETWORD(eaddr);
801 res=dreg-breg; 815 res=dreg-breg;
802 SETSTATUSD(dreg,breg,res) 816 SETSTATUSD(dreg,breg,res)
803 if(iflag==0) SETDREG(res) 817 if(iflag==0) SETDREG(res)
804 }break; 818 }break;
805 case 0x84: /*ANDA immediate*/ IMM8 iareg=iareg&mem[eaddr];SETNZ8(iareg) 819 case 0x84: /*ANDA immediate*/ IMM8 iareg=iareg&mem(eaddr);SETNZ8(iareg)
806 CLV break; 820 CLV break;
807 case 0x85: /*BITA immediate*/ IMM8 tb=iareg&mem[eaddr];SETNZ8(tb) 821 case 0x85: /*BITA immediate*/ IMM8 tb=iareg&mem(eaddr);SETNZ8(tb)
808 CLV break; 822 CLV break;
809 case 0x86: /*LDA immediate*/ IMM8 LOADAC(iareg) CLV SETNZ8(iareg) 823 case 0x86: /*LDA immediate*/ IMM8 LOADAC(iareg) CLV SETNZ8(iareg)
810 break; 824 break;
811 case 0x87: /*STA immediate (for the sake of orthogonality) */ IMM8 825 case 0x87: /*STA immediate (for the sake of orthogonality) */ IMM8
812 SETNZ8(iareg) CLV STOREAC(iareg) break; 826 SETNZ8(iareg) CLV STOREAC(iareg) break;
813 case 0x88: /*EORA immediate*/ IMM8 iareg=iareg^mem[eaddr];SETNZ8(iareg) 827 case 0x88: /*EORA immediate*/ IMM8 iareg=iareg^mem(eaddr);SETNZ8(iareg)
814 CLV break; 828 CLV break;
815 case 0x89: /*ADCA immediate*/ IMM8 tw=iareg+mem[eaddr]+(iccreg&0x01); 829 case 0x89: /*ADCA immediate*/ IMM8 tw=iareg+mem(eaddr)+(iccreg&0x01);
816 SETSTATUS(iareg,mem[eaddr],tw) 830 SETSTATUS(iareg,mem(eaddr),tw)
817 iareg=tw;break; 831 iareg=tw;break;
818 case 0x8A: /*ORA immediate*/ IMM8 iareg=iareg|mem[eaddr];SETNZ8(iareg) 832 case 0x8A: /*ORA immediate*/ IMM8 iareg=iareg|mem(eaddr);SETNZ8(iareg)
819 CLV break; 833 CLV break;
820 case 0x8B: /*ADDA immediate*/ IMM8 tw=iareg+mem[eaddr]; 834 case 0x8B: /*ADDA immediate*/ IMM8 tw=iareg+mem(eaddr);
821 SETSTATUS(iareg,mem[eaddr],tw) 835 SETSTATUS(iareg,mem(eaddr),tw)
822 iareg=tw;break; 836 iareg=tw;break;
823 case 0x8C: /*CMPX (CMPY CMPS) immediate */ IMM16 837 case 0x8C: /*CMPX (CMPY CMPS) immediate */ IMM16
824 {unsigned long dreg,breg,res; 838 {unsigned long dreg,breg,res;
825 if(iflag==0)dreg=ixreg;else if(iflag==1) 839 if(iflag==0)dreg=ixreg;else if(iflag==1)
826 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); 840 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
833 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else 847 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
834 iyreg=tw;break; 848 iyreg=tw;break;
835 case 0x8F: /* STX (STY) immediate (orthogonality) */ IMM16 849 case 0x8F: /* STX (STY) immediate (orthogonality) */ IMM16
836 if(!iflag) tw=ixreg; else tw=iyreg; 850 if(!iflag) tw=ixreg; else tw=iyreg;
837 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; 851 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
838 case 0x90: /*SUBA direct*/ DIRECT tw=iareg-mem[eaddr]; 852 case 0x90: /*SUBA direct*/ DIRECT tw=iareg-mem(eaddr);
839 SETSTATUS(iareg,mem[eaddr],tw) 853 SETSTATUS(iareg,mem(eaddr),tw)
840 iareg=tw;break; 854 iareg=tw;break;
841 case 0x91: /*CMPA direct*/ DIRECT tw=iareg-mem[eaddr]; 855 case 0x91: /*CMPA direct*/ DIRECT tw=iareg-mem(eaddr);
842 SETSTATUS(iareg,mem[eaddr],tw) break; 856 SETSTATUS(iareg,mem(eaddr),tw) break;
843 case 0x92: /*SBCA direct*/ DIRECT tw=iareg-mem[eaddr]-(iccreg&0x01); 857 case 0x92: /*SBCA direct*/ DIRECT tw=iareg-mem(eaddr)-(iccreg&0x01);
844 SETSTATUS(iareg,mem[eaddr],tw) 858 SETSTATUS(iareg,mem(eaddr),tw)
845 iareg=tw;break; 859 iareg=tw;break;
846 case 0x93: /*SUBD (CMPD CMPU) direct*/ DIRECT 860 case 0x93: /*SUBD (CMPD CMPU) direct*/ DIRECT
847 {unsigned long res,dreg,breg; 861 {unsigned long res,dreg,breg;
848 if(iflag==2)dreg=iureg;else dreg=GETDREG; 862 if(iflag==2)dreg=iureg;else dreg=GETDREG;
849 breg=GETWORD(eaddr); 863 breg=GETWORD(eaddr);
850 res=dreg-breg; 864 res=dreg-breg;
851 SETSTATUSD(dreg,breg,res) 865 SETSTATUSD(dreg,breg,res)
852 if(iflag==0) SETDREG(res) 866 if(iflag==0) SETDREG(res)
853 }break; 867 }break;
854 case 0x94: /*ANDA direct*/ DIRECT iareg=iareg&mem[eaddr];SETNZ8(iareg) 868 case 0x94: /*ANDA direct*/ DIRECT iareg=iareg&mem(eaddr);SETNZ8(iareg)
855 CLV break; 869 CLV break;
856 case 0x95: /*BITA direct*/ DIRECT tb=iareg&mem[eaddr];SETNZ8(tb) 870 case 0x95: /*BITA direct*/ DIRECT tb=iareg&mem(eaddr);SETNZ8(tb)
857 CLV break; 871 CLV break;
858 case 0x96: /*LDA direct*/ DIRECT LOADAC(iareg) CLV SETNZ8(iareg) 872 case 0x96: /*LDA direct*/ DIRECT LOADAC(iareg) CLV SETNZ8(iareg)
859 break; 873 break;
860 case 0x97: /*STA direct */ DIRECT 874 case 0x97: /*STA direct */ DIRECT
861 SETNZ8(iareg) CLV STOREAC(iareg) break; 875 SETNZ8(iareg) CLV STOREAC(iareg) break;
862 case 0x98: /*EORA direct*/ DIRECT iareg=iareg^mem[eaddr];SETNZ8(iareg) 876 case 0x98: /*EORA direct*/ DIRECT iareg=iareg^mem(eaddr);SETNZ8(iareg)
863 CLV break; 877 CLV break;
864 case 0x99: /*ADCA direct*/ DIRECT tw=iareg+mem[eaddr]+(iccreg&0x01); 878 case 0x99: /*ADCA direct*/ DIRECT tw=iareg+mem(eaddr)+(iccreg&0x01);
865 SETSTATUS(iareg,mem[eaddr],tw) 879 SETSTATUS(iareg,mem(eaddr),tw)
866 iareg=tw;break; 880 iareg=tw;break;
867 case 0x9A: /*ORA direct*/ DIRECT iareg=iareg|mem[eaddr];SETNZ8(iareg) 881 case 0x9A: /*ORA direct*/ DIRECT iareg=iareg|mem(eaddr);SETNZ8(iareg)
868 CLV break; 882 CLV break;
869 case 0x9B: /*ADDA direct*/ DIRECT tw=iareg+mem[eaddr]; 883 case 0x9B: /*ADDA direct*/ DIRECT tw=iareg+mem(eaddr);
870 SETSTATUS(iareg,mem[eaddr],tw) 884 SETSTATUS(iareg,mem(eaddr),tw)
871 iareg=tw;break; 885 iareg=tw;break;
872 case 0x9C: /*CMPX (CMPY CMPS) direct */ DIRECT 886 case 0x9C: /*CMPX (CMPY CMPS) direct */ DIRECT
873 {unsigned long dreg,breg,res; 887 {unsigned long dreg,breg,res;
874 if(iflag==0)dreg=ixreg;else if(iflag==1) 888 if(iflag==0)dreg=ixreg;else if(iflag==1)
875 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); 889 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
882 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else 896 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
883 iyreg=tw;break; 897 iyreg=tw;break;
884 case 0x9F: /* STX (STY) direct */ DIRECT 898 case 0x9F: /* STX (STY) direct */ DIRECT
885 if(!iflag) tw=ixreg; else tw=iyreg; 899 if(!iflag) tw=ixreg; else tw=iyreg;
886 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; 900 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
887 case 0xA0: /*SUBA indexed*/ tw=iareg-mem[eaddr]; 901 case 0xA0: /*SUBA indexed*/ tw=iareg-mem(eaddr);
888 SETSTATUS(iareg,mem[eaddr],tw) 902 SETSTATUS(iareg,mem(eaddr),tw)
889 iareg=tw;break; 903 iareg=tw;break;
890 case 0xA1: /*CMPA indexed*/ tw=iareg-mem[eaddr]; 904 case 0xA1: /*CMPA indexed*/ tw=iareg-mem(eaddr);
891 SETSTATUS(iareg,mem[eaddr],tw) break; 905 SETSTATUS(iareg,mem(eaddr),tw) break;
892 case 0xA2: /*SBCA indexed*/ tw=iareg-mem[eaddr]-(iccreg&0x01); 906 case 0xA2: /*SBCA indexed*/ tw=iareg-mem(eaddr)-(iccreg&0x01);
893 SETSTATUS(iareg,mem[eaddr],tw) 907 SETSTATUS(iareg,mem(eaddr),tw)
894 iareg=tw;break; 908 iareg=tw;break;
895 case 0xA3: /*SUBD (CMPD CMPU) indexed*/ 909 case 0xA3: /*SUBD (CMPD CMPU) indexed*/
896 {unsigned long res,dreg,breg; 910 {unsigned long res,dreg,breg;
897 if(iflag==2)dreg=iureg;else dreg=GETDREG; 911 if(iflag==2)dreg=iureg;else dreg=GETDREG;
898 breg=GETWORD(eaddr); 912 breg=GETWORD(eaddr);
899 res=dreg-breg; 913 res=dreg-breg;
900 SETSTATUSD(dreg,breg,res) 914 SETSTATUSD(dreg,breg,res)
901 if(iflag==0) SETDREG(res) 915 if(iflag==0) SETDREG(res)
902 }break; 916 }break;
903 case 0xA4: /*ANDA indexed*/ iareg=iareg&mem[eaddr];SETNZ8(iareg) 917 case 0xA4: /*ANDA indexed*/ iareg=iareg&mem(eaddr);SETNZ8(iareg)
904 CLV break; 918 CLV break;
905 case 0xA5: /*BITA indexed*/ tb=iareg&mem[eaddr];SETNZ8(tb) 919 case 0xA5: /*BITA indexed*/ tb=iareg&mem(eaddr);SETNZ8(tb)
906 CLV break; 920 CLV break;
907 case 0xA6: /*LDA indexed*/ LOADAC(iareg) CLV SETNZ8(iareg) 921 case 0xA6: /*LDA indexed*/ LOADAC(iareg) CLV SETNZ8(iareg)
908 break; 922 break;
909 case 0xA7: /*STA indexed */ 923 case 0xA7: /*STA indexed */
910 SETNZ8(iareg) CLV STOREAC(iareg) break; 924 SETNZ8(iareg) CLV STOREAC(iareg) break;
911 case 0xA8: /*EORA indexed*/ iareg=iareg^mem[eaddr];SETNZ8(iareg) 925 case 0xA8: /*EORA indexed*/ iareg=iareg^mem(eaddr);SETNZ8(iareg)
912 CLV break; 926 CLV break;
913 case 0xA9: /*ADCA indexed*/ tw=iareg+mem[eaddr]+(iccreg&0x01); 927 case 0xA9: /*ADCA indexed*/ tw=iareg+mem(eaddr)+(iccreg&0x01);
914 SETSTATUS(iareg,mem[eaddr],tw) 928 SETSTATUS(iareg,mem(eaddr),tw)
915 iareg=tw;break; 929 iareg=tw;break;
916 case 0xAA: /*ORA indexed*/ iareg=iareg|mem[eaddr];SETNZ8(iareg) 930 case 0xAA: /*ORA indexed*/ iareg=iareg|mem(eaddr);SETNZ8(iareg)
917 CLV break; 931 CLV break;
918 case 0xAB: /*ADDA indexed*/ tw=iareg+mem[eaddr]; 932 case 0xAB: /*ADDA indexed*/ tw=iareg+mem(eaddr);
919 SETSTATUS(iareg,mem[eaddr],tw) 933 SETSTATUS(iareg,mem(eaddr),tw)
920 iareg=tw;break; 934 iareg=tw;break;
921 case 0xAC: /*CMPX (CMPY CMPS) indexed */ 935 case 0xAC: /*CMPX (CMPY CMPS) indexed */
922 {unsigned long dreg,breg,res; 936 {unsigned long dreg,breg,res;
923 if(iflag==0)dreg=ixreg;else if(iflag==1) 937 if(iflag==0)dreg=ixreg;else if(iflag==1)
924 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); 938 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
931 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else 945 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
932 iyreg=tw;break; 946 iyreg=tw;break;
933 case 0xAF: /* STX (STY) indexed */ 947 case 0xAF: /* STX (STY) indexed */
934 if(!iflag) tw=ixreg; else tw=iyreg; 948 if(!iflag) tw=ixreg; else tw=iyreg;
935 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; 949 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
936 case 0xB0: /*SUBA ext*/ EXTENDED tw=iareg-mem[eaddr]; 950 case 0xB0: /*SUBA ext*/ EXTENDED tw=iareg-mem(eaddr);
937 SETSTATUS(iareg,mem[eaddr],tw) 951 SETSTATUS(iareg,mem(eaddr),tw)
938 iareg=tw;break; 952 iareg=tw;break;
939 case 0xB1: /*CMPA ext*/ EXTENDED tw=iareg-mem[eaddr]; 953 case 0xB1: /*CMPA ext*/ EXTENDED tw=iareg-mem(eaddr);
940 SETSTATUS(iareg,mem[eaddr],tw) break; 954 SETSTATUS(iareg,mem(eaddr),tw) break;
941 case 0xB2: /*SBCA ext*/ EXTENDED tw=iareg-mem[eaddr]-(iccreg&0x01); 955 case 0xB2: /*SBCA ext*/ EXTENDED tw=iareg-mem(eaddr)-(iccreg&0x01);
942 SETSTATUS(iareg,mem[eaddr],tw) 956 SETSTATUS(iareg,mem(eaddr),tw)
943 iareg=tw;break; 957 iareg=tw;break;
944 case 0xB3: /*SUBD (CMPD CMPU) ext*/ EXTENDED 958 case 0xB3: /*SUBD (CMPD CMPU) ext*/ EXTENDED
945 {unsigned long res,dreg,breg; 959 {unsigned long res,dreg,breg;
946 if(iflag==2)dreg=iureg;else dreg=GETDREG; 960 if(iflag==2)dreg=iureg;else dreg=GETDREG;
947 breg=GETWORD(eaddr); 961 breg=GETWORD(eaddr);
948 res=dreg-breg; 962 res=dreg-breg;
949 SETSTATUSD(dreg,breg,res) 963 SETSTATUSD(dreg,breg,res)
950 if(iflag==0) SETDREG(res) 964 if(iflag==0) SETDREG(res)
951 }break; 965 }break;
952 case 0xB4: /*ANDA ext*/ EXTENDED iareg=iareg&mem[eaddr];SETNZ8(iareg) 966 case 0xB4: /*ANDA ext*/ EXTENDED iareg=iareg&mem(eaddr);SETNZ8(iareg)
953 CLV break; 967 CLV break;
954 case 0xB5: /*BITA ext*/ EXTENDED tb=iareg&mem[eaddr];SETNZ8(tb) 968 case 0xB5: /*BITA ext*/ EXTENDED tb=iareg&mem(eaddr);SETNZ8(tb)
955 CLV break; 969 CLV break;
956 case 0xB6: /*LDA ext*/ EXTENDED LOADAC(iareg) CLV SETNZ8(iareg) 970 case 0xB6: /*LDA ext*/ EXTENDED LOADAC(iareg) CLV SETNZ8(iareg)
957 break; 971 break;
958 case 0xB7: /*STA ext */ EXTENDED 972 case 0xB7: /*STA ext */ EXTENDED
959 SETNZ8(iareg) CLV STOREAC(iareg) break; 973 SETNZ8(iareg) CLV STOREAC(iareg) break;
960 case 0xB8: /*EORA ext*/ EXTENDED iareg=iareg^mem[eaddr];SETNZ8(iareg) 974 case 0xB8: /*EORA ext*/ EXTENDED iareg=iareg^mem(eaddr);SETNZ8(iareg)
961 CLV break; 975 CLV break;
962 case 0xB9: /*ADCA ext*/ EXTENDED tw=iareg+mem[eaddr]+(iccreg&0x01); 976 case 0xB9: /*ADCA ext*/ EXTENDED tw=iareg+mem(eaddr)+(iccreg&0x01);
963 SETSTATUS(iareg,mem[eaddr],tw) 977 SETSTATUS(iareg,mem(eaddr),tw)
964 iareg=tw;break; 978 iareg=tw;break;
965 case 0xBA: /*ORA ext*/ EXTENDED iareg=iareg|mem[eaddr];SETNZ8(iareg) 979 case 0xBA: /*ORA ext*/ EXTENDED iareg=iareg|mem(eaddr);SETNZ8(iareg)
966 CLV break; 980 CLV break;
967 case 0xBB: /*ADDA ext*/ EXTENDED tw=iareg+mem[eaddr]; 981 case 0xBB: /*ADDA ext*/ EXTENDED tw=iareg+mem(eaddr);
968 SETSTATUS(iareg,mem[eaddr],tw) 982 SETSTATUS(iareg,mem(eaddr),tw)
969 iareg=tw;break; 983 iareg=tw;break;
970 case 0xBC: /*CMPX (CMPY CMPS) ext */ EXTENDED 984 case 0xBC: /*CMPX (CMPY CMPS) ext */ EXTENDED
971 {unsigned long dreg,breg,res; 985 {unsigned long dreg,breg,res;
972 if(iflag==0)dreg=ixreg;else if(iflag==1) 986 if(iflag==0)dreg=ixreg;else if(iflag==1)
973 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr); 987 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
980 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else 994 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
981 iyreg=tw;break; 995 iyreg=tw;break;
982 case 0xBF: /* STX (STY) ext */ EXTENDED 996 case 0xBF: /* STX (STY) ext */ EXTENDED
983 if(!iflag) tw=ixreg; else tw=iyreg; 997 if(!iflag) tw=ixreg; else tw=iyreg;
984 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; 998 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
985 case 0xC0: /*SUBB immediate*/ IMM8 tw=ibreg-mem[eaddr]; 999 case 0xC0: /*SUBB immediate*/ IMM8 tw=ibreg-mem(eaddr);
986 SETSTATUS(ibreg,mem[eaddr],tw) 1000 SETSTATUS(ibreg,mem(eaddr),tw)
987 ibreg=tw;break; 1001 ibreg=tw;break;
988 case 0xC1: /*CMPB immediate*/ IMM8 tw=ibreg-mem[eaddr]; 1002 case 0xC1: /*CMPB immediate*/ IMM8 tw=ibreg-mem(eaddr);
989 SETSTATUS(ibreg,mem[eaddr],tw) break; 1003 SETSTATUS(ibreg,mem(eaddr),tw) break;
990 case 0xC2: /*SBCB immediate*/ IMM8 tw=ibreg-mem[eaddr]-(iccreg&0x01); 1004 case 0xC2: /*SBCB immediate*/ IMM8 tw=ibreg-mem(eaddr)-(iccreg&0x01);
991 SETSTATUS(ibreg,mem[eaddr],tw) 1005 SETSTATUS(ibreg,mem(eaddr),tw)
992 ibreg=tw;break; 1006 ibreg=tw;break;
993 case 0xC3: /*ADDD immediate*/ IMM16 1007 case 0xC3: /*ADDD immediate*/ IMM16
994 {unsigned long res,dreg,breg; 1008 {unsigned long res,dreg,breg;
995 dreg=GETDREG; 1009 dreg=GETDREG;
996 breg=GETWORD(eaddr); 1010 breg=GETWORD(eaddr);
997 res=dreg+breg; 1011 res=dreg+breg;
998 SETSTATUSD(dreg,breg,res) 1012 SETSTATUSD(dreg,breg,res)
999 SETDREG(res) 1013 SETDREG(res)
1000 }break; 1014 }break;
1001 case 0xC4: /*ANDB immediate*/ IMM8 ibreg=ibreg&mem[eaddr];SETNZ8(ibreg) 1015 case 0xC4: /*ANDB immediate*/ IMM8 ibreg=ibreg&mem(eaddr);SETNZ8(ibreg)
1002 CLV break; 1016 CLV break;
1003 case 0xC5: /*BITB immediate*/ IMM8 tb=ibreg&mem[eaddr];SETNZ8(tb) 1017 case 0xC5: /*BITB immediate*/ IMM8 tb=ibreg&mem(eaddr);SETNZ8(tb)
1004 CLV break; 1018 CLV break;
1005 case 0xC6: /*LDB immediate*/ IMM8 LOADAC(ibreg) CLV SETNZ8(ibreg) 1019 case 0xC6: /*LDB immediate*/ IMM8 LOADAC(ibreg) CLV SETNZ8(ibreg)
1006 break; 1020 break;
1007 case 0xC7: /*STB immediate (for the sake of orthogonality) */ IMM8 1021 case 0xC7: /*STB immediate (for the sake of orthogonality) */ IMM8
1008 SETNZ8(ibreg) CLV STOREAC(ibreg) break; 1022 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
1009 case 0xC8: /*EORB immediate*/ IMM8 ibreg=ibreg^mem[eaddr];SETNZ8(ibreg) 1023 case 0xC8: /*EORB immediate*/ IMM8 ibreg=ibreg^mem(eaddr);SETNZ8(ibreg)
1010 CLV break; 1024 CLV break;
1011 case 0xC9: /*ADCB immediate*/ IMM8 tw=ibreg+mem[eaddr]+(iccreg&0x01); 1025 case 0xC9: /*ADCB immediate*/ IMM8 tw=ibreg+mem(eaddr)+(iccreg&0x01);
1012 SETSTATUS(ibreg,mem[eaddr],tw) 1026 SETSTATUS(ibreg,mem(eaddr),tw)
1013 ibreg=tw;break; 1027 ibreg=tw;break;
1014 case 0xCA: /*ORB immediate*/ IMM8 ibreg=ibreg|mem[eaddr];SETNZ8(ibreg) 1028 case 0xCA: /*ORB immediate*/ IMM8 ibreg=ibreg|mem(eaddr);SETNZ8(ibreg)
1015 CLV break; 1029 CLV break;
1016 case 0xCB: /*ADDB immediate*/ IMM8 tw=ibreg+mem[eaddr]; 1030 case 0xCB: /*ADDB immediate*/ IMM8 tw=ibreg+mem(eaddr);
1017 SETSTATUS(ibreg,mem[eaddr],tw) 1031 SETSTATUS(ibreg,mem(eaddr),tw)
1018 ibreg=tw;break; 1032 ibreg=tw;break;
1019 case 0xCC: /*LDD immediate */ IMM16 tw=GETWORD(eaddr);SETNZ16(tw) 1033 case 0xCC: /*LDD immediate */ IMM16 tw=GETWORD(eaddr);SETNZ16(tw)
1020 CLV SETDREG(tw) break; 1034 CLV SETDREG(tw) break;
1021 case 0xCD: /*STD immediate (orthogonality) */ IMM16 1035 case 0xCD: /*STD immediate (orthogonality) */ IMM16
1022 tw=GETDREG; SETNZ16(tw) CLV 1036 tw=GETDREG; SETNZ16(tw) CLV
1025 CLV SETNZ16(tw) if(!iflag)iureg=tw; else 1039 CLV SETNZ16(tw) if(!iflag)iureg=tw; else
1026 isreg=tw;break; 1040 isreg=tw;break;
1027 case 0xCF: /* STU (STS) immediate (orthogonality) */ IMM16 1041 case 0xCF: /* STU (STS) immediate (orthogonality) */ IMM16
1028 if(!iflag) tw=iureg; else tw=isreg; 1042 if(!iflag) tw=iureg; else tw=isreg;
1029 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; 1043 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
1030 case 0xD0: /*SUBB direct*/ DIRECT tw=ibreg-mem[eaddr]; 1044 case 0xD0: /*SUBB direct*/ DIRECT tw=ibreg-mem(eaddr);
1031 SETSTATUS(ibreg,mem[eaddr],tw) 1045 SETSTATUS(ibreg,mem(eaddr),tw)
1032 ibreg=tw;break; 1046 ibreg=tw;break;
1033 case 0xD1: /*CMPB direct*/ DIRECT tw=ibreg-mem[eaddr]; 1047 case 0xD1: /*CMPB direct*/ DIRECT tw=ibreg-mem(eaddr);
1034 SETSTATUS(ibreg,mem[eaddr],tw) break; 1048 SETSTATUS(ibreg,mem(eaddr),tw) break;
1035 case 0xD2: /*SBCB direct*/ DIRECT tw=ibreg-mem[eaddr]-(iccreg&0x01); 1049 case 0xD2: /*SBCB direct*/ DIRECT tw=ibreg-mem(eaddr)-(iccreg&0x01);
1036 SETSTATUS(ibreg,mem[eaddr],tw) 1050 SETSTATUS(ibreg,mem(eaddr),tw)
1037 ibreg=tw;break; 1051 ibreg=tw;break;
1038 case 0xD3: /*ADDD direct*/ DIRECT 1052 case 0xD3: /*ADDD direct*/ DIRECT
1039 {unsigned long res,dreg,breg; 1053 {unsigned long res,dreg,breg;
1040 dreg=GETDREG; 1054 dreg=GETDREG;
1041 breg=GETWORD(eaddr); 1055 breg=GETWORD(eaddr);
1042 res=dreg+breg; 1056 res=dreg+breg;
1043 SETSTATUSD(dreg,breg,res) 1057 SETSTATUSD(dreg,breg,res)
1044 SETDREG(res) 1058 SETDREG(res)
1045 }break; 1059 }break;
1046 case 0xD4: /*ANDB direct*/ DIRECT ibreg=ibreg&mem[eaddr];SETNZ8(ibreg) 1060 case 0xD4: /*ANDB direct*/ DIRECT ibreg=ibreg&mem(eaddr);SETNZ8(ibreg)
1047 CLV break; 1061 CLV break;
1048 case 0xD5: /*BITB direct*/ DIRECT tb=ibreg&mem[eaddr];SETNZ8(tb) 1062 case 0xD5: /*BITB direct*/ DIRECT tb=ibreg&mem(eaddr);SETNZ8(tb)
1049 CLV break; 1063 CLV break;
1050 case 0xD6: /*LDB direct*/ DIRECT LOADAC(ibreg) CLV SETNZ8(ibreg) 1064 case 0xD6: /*LDB direct*/ DIRECT LOADAC(ibreg) CLV SETNZ8(ibreg)
1051 break; 1065 break;
1052 case 0xD7: /*STB direct */ DIRECT 1066 case 0xD7: /*STB direct */ DIRECT
1053 SETNZ8(ibreg) CLV STOREAC(ibreg) break; 1067 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
1054 case 0xD8: /*EORB direct*/ DIRECT ibreg=ibreg^mem[eaddr];SETNZ8(ibreg) 1068 case 0xD8: /*EORB direct*/ DIRECT ibreg=ibreg^mem(eaddr);SETNZ8(ibreg)
1055 CLV break; 1069 CLV break;
1056 case 0xD9: /*ADCB direct*/ DIRECT tw=ibreg+mem[eaddr]+(iccreg&0x01); 1070 case 0xD9: /*ADCB direct*/ DIRECT tw=ibreg+mem(eaddr)+(iccreg&0x01);
1057 SETSTATUS(ibreg,mem[eaddr],tw) 1071 SETSTATUS(ibreg,mem(eaddr),tw)
1058 ibreg=tw;break; 1072 ibreg=tw;break;
1059 case 0xDA: /*ORB direct*/ DIRECT ibreg=ibreg|mem[eaddr];SETNZ8(ibreg) 1073 case 0xDA: /*ORB direct*/ DIRECT ibreg=ibreg|mem(eaddr);SETNZ8(ibreg)
1060 CLV break; 1074 CLV break;
1061 case 0xDB: /*ADDB direct*/ DIRECT tw=ibreg+mem[eaddr]; 1075 case 0xDB: /*ADDB direct*/ DIRECT tw=ibreg+mem(eaddr);
1062 SETSTATUS(ibreg,mem[eaddr],tw) 1076 SETSTATUS(ibreg,mem(eaddr),tw)
1063 ibreg=tw;break; 1077 ibreg=tw;break;
1064 case 0xDC: /*LDD direct */ DIRECT tw=GETWORD(eaddr);SETNZ16(tw) 1078 case 0xDC: /*LDD direct */ DIRECT tw=GETWORD(eaddr);SETNZ16(tw)
1065 CLV SETDREG(tw) break; 1079 CLV SETDREG(tw) break;
1066 case 0xDD: /*STD direct */ DIRECT 1080 case 0xDD: /*STD direct */ DIRECT
1067 tw=GETDREG; SETNZ16(tw) CLV 1081 tw=GETDREG; SETNZ16(tw) CLV
1070 CLV SETNZ16(tw) if(!iflag)iureg=tw; else 1084 CLV SETNZ16(tw) if(!iflag)iureg=tw; else
1071 isreg=tw;break; 1085 isreg=tw;break;
1072 case 0xDF: /* STU (STS) direct */ DIRECT 1086 case 0xDF: /* STU (STS) direct */ DIRECT
1073 if(!iflag) tw=iureg; else tw=isreg; 1087 if(!iflag) tw=iureg; else tw=isreg;
1074 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; 1088 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
1075 case 0xE0: /*SUBB indexed*/ tw=ibreg-mem[eaddr]; 1089 case 0xE0: /*SUBB indexed*/ tw=ibreg-mem(eaddr);
1076 SETSTATUS(ibreg,mem[eaddr],tw) 1090 SETSTATUS(ibreg,mem(eaddr),tw)
1077 ibreg=tw;break; 1091 ibreg=tw;break;
1078 case 0xE1: /*CMPB indexed*/ tw=ibreg-mem[eaddr]; 1092 case 0xE1: /*CMPB indexed*/ tw=ibreg-mem(eaddr);
1079 SETSTATUS(ibreg,mem[eaddr],tw) break; 1093 SETSTATUS(ibreg,mem(eaddr),tw) break;
1080 case 0xE2: /*SBCB indexed*/ tw=ibreg-mem[eaddr]-(iccreg&0x01); 1094 case 0xE2: /*SBCB indexed*/ tw=ibreg-mem(eaddr)-(iccreg&0x01);
1081 SETSTATUS(ibreg,mem[eaddr],tw) 1095 SETSTATUS(ibreg,mem(eaddr),tw)
1082 ibreg=tw;break; 1096 ibreg=tw;break;
1083 case 0xE3: /*ADDD indexed*/ 1097 case 0xE3: /*ADDD indexed*/
1084 {unsigned long res,dreg,breg; 1098 {unsigned long res,dreg,breg;
1085 dreg=GETDREG; 1099 dreg=GETDREG;
1086 breg=GETWORD(eaddr); 1100 breg=GETWORD(eaddr);
1087 res=dreg+breg; 1101 res=dreg+breg;
1088 SETSTATUSD(dreg,breg,res) 1102 SETSTATUSD(dreg,breg,res)
1089 SETDREG(res) 1103 SETDREG(res)
1090 }break; 1104 }break;
1091 case 0xE4: /*ANDB indexed*/ ibreg=ibreg&mem[eaddr];SETNZ8(ibreg) 1105 case 0xE4: /*ANDB indexed*/ ibreg=ibreg&mem(eaddr);SETNZ8(ibreg)
1092 CLV break; 1106 CLV break;
1093 case 0xE5: /*BITB indexed*/ tb=ibreg&mem[eaddr];SETNZ8(tb) 1107 case 0xE5: /*BITB indexed*/ tb=ibreg&mem(eaddr);SETNZ8(tb)
1094 CLV break; 1108 CLV break;
1095 case 0xE6: /*LDB indexed*/ LOADAC(ibreg) CLV SETNZ8(ibreg) 1109 case 0xE6: /*LDB indexed*/ LOADAC(ibreg) CLV SETNZ8(ibreg)
1096 break; 1110 break;
1097 case 0xE7: /*STB indexed */ 1111 case 0xE7: /*STB indexed */
1098 SETNZ8(ibreg) CLV STOREAC(ibreg) break; 1112 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
1099 case 0xE8: /*EORB indexed*/ ibreg=ibreg^mem[eaddr];SETNZ8(ibreg) 1113 case 0xE8: /*EORB indexed*/ ibreg=ibreg^mem(eaddr);SETNZ8(ibreg)
1100 CLV break; 1114 CLV break;
1101 case 0xE9: /*ADCB indexed*/ tw=ibreg+mem[eaddr]+(iccreg&0x01); 1115 case 0xE9: /*ADCB indexed*/ tw=ibreg+mem(eaddr)+(iccreg&0x01);
1102 SETSTATUS(ibreg,mem[eaddr],tw) 1116 SETSTATUS(ibreg,mem(eaddr),tw)
1103 ibreg=tw;break; 1117 ibreg=tw;break;
1104 case 0xEA: /*ORB indexed*/ ibreg=ibreg|mem[eaddr];SETNZ8(ibreg) 1118 case 0xEA: /*ORB indexed*/ ibreg=ibreg|mem(eaddr);SETNZ8(ibreg)
1105 CLV break; 1119 CLV break;
1106 case 0xEB: /*ADDB indexed*/ tw=ibreg+mem[eaddr]; 1120 case 0xEB: /*ADDB indexed*/ tw=ibreg+mem(eaddr);
1107 SETSTATUS(ibreg,mem[eaddr],tw) 1121 SETSTATUS(ibreg,mem(eaddr),tw)
1108 ibreg=tw;break; 1122 ibreg=tw;break;
1109 case 0xEC: /*LDD indexed */ tw=GETWORD(eaddr);SETNZ16(tw) 1123 case 0xEC: /*LDD indexed */ tw=GETWORD(eaddr);SETNZ16(tw)
1110 CLV SETDREG(tw) break; 1124 CLV SETDREG(tw) break;
1111 case 0xED: /*STD indexed */ 1125 case 0xED: /*STD indexed */
1112 tw=GETDREG; SETNZ16(tw) CLV 1126 tw=GETDREG; SETNZ16(tw) CLV
1115 CLV SETNZ16(tw) if(!iflag)iureg=tw; else 1129 CLV SETNZ16(tw) if(!iflag)iureg=tw; else
1116 isreg=tw;break; 1130 isreg=tw;break;
1117 case 0xEF: /* STU (STS) indexed */ 1131 case 0xEF: /* STU (STS) indexed */
1118 if(!iflag) tw=iureg; else tw=isreg; 1132 if(!iflag) tw=iureg; else tw=isreg;
1119 CLV SETNZ16(tw) SETWORD(eaddr,tw) break; 1133 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
1120 case 0xF0: /*SUBB ext*/ EXTENDED tw=ibreg-mem[eaddr]; 1134 case 0xF0: /*SUBB ext*/ EXTENDED tw=ibreg-mem(eaddr);
1121 SETSTATUS(ibreg,mem[eaddr],tw) 1135 SETSTATUS(ibreg,mem(eaddr),tw)
1122 ibreg=tw;break; 1136 ibreg=tw;break;
1123 case 0xF1: /*CMPB ext*/ EXTENDED tw=ibreg-mem[eaddr]; 1137 case 0xF1: /*CMPB ext*/ EXTENDED tw=ibreg-mem(eaddr);
1124 SETSTATUS(ibreg,mem[eaddr],tw) break; 1138 SETSTATUS(ibreg,mem(eaddr),tw) break;
1125 case 0xF2: /*SBCB ext*/ EXTENDED tw=ibreg-mem[eaddr]-(iccreg&0x01); 1139 case 0xF2: /*SBCB ext*/ EXTENDED tw=ibreg-mem(eaddr)-(iccreg&0x01);
1126 SETSTATUS(ibreg,mem[eaddr],tw) 1140 SETSTATUS(ibreg,mem(eaddr),tw)
1127 ibreg=tw;break; 1141 ibreg=tw;break;
1128 case 0xF3: /*ADDD ext*/ EXTENDED 1142 case 0xF3: /*ADDD ext*/ EXTENDED
1129 {unsigned long res,dreg,breg; 1143 {unsigned long res,dreg,breg;
1130 dreg=GETDREG; 1144 dreg=GETDREG;
1131 breg=GETWORD(eaddr); 1145 breg=GETWORD(eaddr);
1132 res=dreg+breg; 1146 res=dreg+breg;
1133 SETSTATUSD(dreg,breg,res) 1147 SETSTATUSD(dreg,breg,res)
1134 SETDREG(res) 1148 SETDREG(res)
1135 }break; 1149 }break;
1136 case 0xF4: /*ANDB ext*/ EXTENDED ibreg=ibreg&mem[eaddr];SETNZ8(ibreg) 1150 case 0xF4: /*ANDB ext*/ EXTENDED ibreg=ibreg&mem(eaddr);SETNZ8(ibreg)
1137 CLV break; 1151 CLV break;
1138 case 0xF5: /*BITB ext*/ EXTENDED tb=ibreg&mem[eaddr];SETNZ8(tb) 1152 case 0xF5: /*BITB ext*/ EXTENDED tb=ibreg&mem(eaddr);SETNZ8(tb)
1139 CLV break; 1153 CLV break;
1140 case 0xF6: /*LDB ext*/ EXTENDED LOADAC(ibreg) CLV SETNZ8(ibreg) 1154 case 0xF6: /*LDB ext*/ EXTENDED LOADAC(ibreg) CLV SETNZ8(ibreg)
1141 break; 1155 break;
1142 case 0xF7: /*STB ext */ EXTENDED 1156 case 0xF7: /*STB ext */ EXTENDED
1143 SETNZ8(ibreg) CLV STOREAC(ibreg) break; 1157 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
1144 case 0xF8: /*EORB ext*/ EXTENDED ibreg=ibreg^mem[eaddr];SETNZ8(ibreg) 1158 case 0xF8: /*EORB ext*/ EXTENDED ibreg=ibreg^mem(eaddr);SETNZ8(ibreg)
1145 CLV break; 1159 CLV break;
1146 case 0xF9: /*ADCB ext*/ EXTENDED tw=ibreg+mem[eaddr]+(iccreg&0x01); 1160 case 0xF9: /*ADCB ext*/ EXTENDED tw=ibreg+mem(eaddr)+(iccreg&0x01);
1147 SETSTATUS(ibreg,mem[eaddr],tw) 1161 SETSTATUS(ibreg,mem(eaddr),tw)
1148 ibreg=tw;break; 1162 ibreg=tw;break;
1149 case 0xFA: /*ORB ext*/ EXTENDED ibreg=ibreg|mem[eaddr];SETNZ8(ibreg) 1163 case 0xFA: /*ORB ext*/ EXTENDED ibreg=ibreg|mem(eaddr);SETNZ8(ibreg)
1150 CLV break; 1164 CLV break;
1151 case 0xFB: /*ADDB ext*/ EXTENDED tw=ibreg+mem[eaddr]; 1165 case 0xFB: /*ADDB ext*/ EXTENDED tw=ibreg+mem(eaddr);
1152 SETSTATUS(ibreg,mem[eaddr],tw) 1166 SETSTATUS(ibreg,mem(eaddr),tw)
1153 ibreg=tw;break; 1167 ibreg=tw;break;
1154 case 0xFC: /*LDD ext */ EXTENDED tw=GETWORD(eaddr);SETNZ16(tw) 1168 case 0xFC: /*LDD ext */ EXTENDED tw=GETWORD(eaddr);SETNZ16(tw)
1155 CLV SETDREG(tw) break; 1169 CLV SETDREG(tw) break;
1156 case 0xFD: /*STD ext */ EXTENDED 1170 case 0xFD: /*STD ext */ EXTENDED
1157 tw=GETDREG; SETNZ16(tw) CLV 1171 tw=GETDREG; SETNZ16(tw) CLV