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1 // initialize section
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2 #include "types.h"
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3 #include "param.h"
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4 #include "arm.h"
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5 #include "mmu.h"
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6 #include "defs.h"
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7 #include "memlayout.h"
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8
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9 void _uart_putc(int c)
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10 {
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11 volatile uint8 * uart0 = (uint8*)UART0;
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12 *uart0 = c;
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13 }
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14
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15
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16 void _puts (char *s)
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17 {
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18 while (*s != '\0') {
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19 _uart_putc(*s);
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20 s++;
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21 }
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22 }
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23
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24 void _putint (char *prefix, uint val, char* suffix)
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25 {
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26 char* arr = "0123456789ABCDEF";
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27 int idx;
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28
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29 if (prefix) {
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30 _puts(prefix);
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31 }
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32
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33 for (idx = sizeof(val) * 8 - 4; idx >= 0; idx -= 4) {
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34 _uart_putc(arr[(val >> idx) & 0x0F]);
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35 }
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36
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37 if (suffix) {
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38 _puts(suffix);
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39 }
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40 }
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41
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42
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43 // kernel page table, reserved in the kernel.ld
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44 extern uint32 _kernel_pgtbl;
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45 extern uint32 _user_pgtbl;
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46
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47 uint32 *kernel_pgtbl = &_kernel_pgtbl;
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48 uint32 *user_pgtbl = &_user_pgtbl;
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49
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50 #define PDE_SHIFT 20
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51
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52 uint32 get_pde (uint32 virt)
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53 {
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54 virt >>= PDE_SHIFT;
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55 return kernel_pgtbl[virt];
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56 }
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57
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58 // setup the boot page table: dev_mem whether it is device memory
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59 void set_bootpgtbl (uint32 virt, uint32 phy, uint len, int dev_mem )
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60 {
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61 uint32 pde;
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62 int idx;
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63
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64 // convert all the parameters to indexes
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65 virt >>= PDE_SHIFT;
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66 phy >>= PDE_SHIFT;
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67 len >>= PDE_SHIFT;
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68
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69 for (idx = 0; idx < len; idx++) {
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70 pde = (phy << PDE_SHIFT);
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71
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72 if (!dev_mem) {
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73 // normal memory, make it kernel-only, cachable, bufferable
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74 pde |= (AP_KO << 10) | PE_CACHE | PE_BUF | KPDE_TYPE;
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75 } else {
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76 // device memory, make it non-cachable and non-bufferable
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77 pde |= (AP_KO << 10) | KPDE_TYPE;
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78 }
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79
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80 // use different page table for user/kernel space
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81 if (virt < NUM_UPDE) {
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82 user_pgtbl[virt] = pde;
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83 } else {
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84 kernel_pgtbl[virt] = pde;
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85 }
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86
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87 virt++;
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88 phy++;
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89 }
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90 }
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91
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92 static void _flush_all (void)
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93 {
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94 uint val = 0;
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95
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96 // flush all TLB
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97 asm("MCR p15, 0, %[r], c8, c7, 0" : :[r]"r" (val):);
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98
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99 // invalid entire data and instruction cache
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100 // asm ("MCR p15,0,%[r],c7,c5,0": :[r]"r" (val):);
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101 // asm ("MCR p15,0,%[r],c7,c6,0": :[r]"r" (val):);
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102 }
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103
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104 void load_pgtlb (uint32* kern_pgtbl, uint32* user_pgtbl)
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105 {
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106 uint ret;
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107 char arch;
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108 uint val;
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109
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110 // read the main id register to make sure we are running on ARMv6
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111 asm("MRC p15, 0, %[r], c0, c0, 0": [r]"=r" (ret)::);
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112
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113 if (ret >> 24 == 0x41) {
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114 //_puts ("ARM-based CPU\n");
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115 }
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116
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117 arch = (ret >> 16) & 0x0F;
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118
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119 if ((arch != 7) && (arch != 0xF)) {
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120 _puts ("need AARM v6 or higher\n");
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121 }
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122
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123 // we need to check the cache/tlb etc., but let's skip it for now
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124
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125 // set domain access control: all domain will be checked for permission
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126 val = 0x55555555;
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127 asm("MCR p15, 0, %[v], c3, c0, 0": :[v]"r" (val):);
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128
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129 // set the page table base registers. We use two page tables: TTBR0
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130 // for user space and TTBR1 for kernel space
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131 val = 32 - UADDR_BITS;
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132 asm("MCR p15, 0, %[v], c2, c0, 2": :[v]"r" (val):);
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133
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134 // set the kernel page table
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135 val = (uint)kernel_pgtbl | 0x00;
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136 asm("MCR p15, 0, %[v], c2, c0, 1": :[v]"r" (val):);
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137
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138 // set the user page table
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139 val = (uint)user_pgtbl | 0x00;
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140 asm("MCR p15, 0, %[v], c2, c0, 0": :[v]"r" (val):);
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141
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142 // ok, enable paging using read/modify/write
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143 asm("MRC p15, 0, %[r], c1, c0, 0": [r]"=r" (val)::);
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144
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145 val |= 0x80300D; // enable MMU, cache, write buffer, high vector tbl,
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146 // disable subpage
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147 asm("MCR p15, 0, %[r], c1, c0, 0": :[r]"r" (val):);
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148
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149 _flush_all();
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150 }
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151
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152 extern void * edata_entry;
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153 extern void * svc_stktop;
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154 extern void kmain (void);
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155 extern void jump_stack (void);
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156
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157 extern void * edata;
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158 extern void * end;
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159
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160 // clear the BSS section for the main kernel, see kernel.ld
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161 void clear_bss (void)
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162 {
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163 memset(&edata, 0x00, (uint)&end-(uint)&edata);
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164 }
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165
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166 void start (void)
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167 {
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168 uint32 vectbl;
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169 _puts("starting xv6 for ARM...\n");
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170
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171 // double map the low memory, required to enable paging
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172 // we do not map all the physical memory
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173 set_bootpgtbl(0, 0, INIT_KERNMAP, 0);
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174 set_bootpgtbl(KERNBASE, 0, INIT_KERNMAP, 0);
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175
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176 // vector table is in the middle of first 1MB (0xF000)
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177 vectbl = P2V_WO (VEC_TBL & PDE_MASK);
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178
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179 if (vectbl <= (uint)&end) {
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180 cprintf ("error: vector table overlaps kernel\n");
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181 }
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182
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183 set_bootpgtbl(VEC_TBL, 0, 1 << PDE_SHIFT, 0);
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184 set_bootpgtbl(KERNBASE+DEVBASE, DEVBASE, DEV_MEM_SZ, 1);
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185
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186 load_pgtlb (kernel_pgtbl, user_pgtbl);
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187 jump_stack ();
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188
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189 // We can now call normal kernel functions at high memory
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190 clear_bss ();
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191
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192 kmain ();
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193 }
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