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1 /*****************************************************************
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2 * uart.c
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3 * by Zhiyi Huang, hzy@cs.otago.ac.nz
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4 * University of Otago
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5 *
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6 ********************************************************************/
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7
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8
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9
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10 #include "types.h"
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11 #include "defs.h"
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12 #include "memlayout.h"
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13 #include "traps.h"
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14 #include "arm.h"
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15
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16 #define GPFSEL0 (MMIO_VA+0x200000)
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17 #define GPFSEL1 (MMIO_VA+0x200004)
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18 #define GPFSEL2 (MMIO_VA+0x200008)
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19 #define GPFSEL3 (MMIO_VA+0x20000C)
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20 #define GPFSEL4 (MMIO_VA+0x200010)
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21 #define GPFSEL5 (MMIO_VA+0x200014)
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22 #define GPSET0 (MMIO_VA+0x20001C)
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23 #define GPSET1 (MMIO_VA+0x200020)
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24 #define GPCLR0 (MMIO_VA+0x200028)
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25 #define GPCLR1 (MMIO_VA+0x20002C)
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26 #define GPPUD (MMIO_VA+0x200094)
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27 #define GPPUDCLK0 (MMIO_VA+0x200098)
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28 #define GPPUDCLK1 (MMIO_VA+0x20009C)
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29
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30 #define AUX_IRQ (MMIO_VA+0x215000)
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31 #define AUX_ENABLES (MMIO_VA+0x215004)
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32 #define AUX_MU_IO_REG (MMIO_VA+0x215040)
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33 #define AUX_MU_IER_REG (MMIO_VA+0x215044)
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34 #define AUX_MU_IIR_REG (MMIO_VA+0x215048)
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35 #define AUX_MU_LCR_REG (MMIO_VA+0x21504C)
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36 #define AUX_MU_MCR_REG (MMIO_VA+0x215050)
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37 #define AUX_MU_LSR_REG (MMIO_VA+0x215054)
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38 #define AUX_MU_MSR_REG (MMIO_VA+0x215058)
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39 #define AUX_MU_SCRATCH (MMIO_VA+0x21505C)
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40 #define AUX_MU_CNTL_REG (MMIO_VA+0x215060)
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41 #define AUX_MU_STAT_REG (MMIO_VA+0x215064)
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42 #define AUX_MU_BAUD_REG (MMIO_VA+0x215068)
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43
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44 void
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45 setgpioval(uint pin, uint val)
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46 {
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47 uint sel, ssel, rsel, shift;
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48
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49 if(pin > 53) return;
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50 if(pin >= 32) sel = 1; else sel = 0;
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51 ssel = GPSET0 + (sel << 2);
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52 rsel = GPCLR0 + (sel << 2);
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53 if(sel) shift = (pin - 32) & 0x1f;
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54 else shift = pin & 0x1f;
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55 if(val == 0) outw(rsel, 1<<shift);
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56 else outw(ssel, 1<<shift);
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57 }
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58
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59
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60 void
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61 setgpiofunc(uint pin, uint func)
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62 {
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63 uint sel, data, shift;
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64
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65 if(pin > 53) return;
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66 sel = 0;
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67 while (pin > 10) {
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68 pin = pin - 10;
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69 sel++;
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70 }
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71 sel = (sel << 2) + GPFSEL0;
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72 data = inw(sel);
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73 shift = pin + (pin << 1);
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74 data &= ~(7 << shift);
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75 outw(sel, data);
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76 data |= func << shift;
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77 outw(sel, data);
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78 }
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79
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80
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81 void
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82 uartputc(uint c)
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83 {
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84 if(c=='\n') {
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85 while(1) if(inw(AUX_MU_LSR_REG) & 0x20) break;
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86 outw(AUX_MU_IO_REG, 0x0d); // add CR before LF
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87 }
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88 while(1) if(inw(AUX_MU_LSR_REG) & 0x20) break;
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89 outw(AUX_MU_IO_REG, c);
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90 }
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91
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92 static int
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93 uartgetc(void)
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94 {
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95 if(inw(AUX_MU_LSR_REG)&0x1) return inw(AUX_MU_IO_REG);
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96 else return -1;
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97 }
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98
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99 void
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100 enableirqminiuart(void)
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101 {
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102 intctrlregs *ip;
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103
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104 ip = (intctrlregs *)INT_REGS_BASE;
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105 ip->gpuenable[0] |= (1 << 29); // enable the miniuart through Aux
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106 }
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107
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108
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109 void
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110 miniuartintr(void)
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111 {
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112 consoleintr(uartgetc);
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113 }
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114
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115 void
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116 uartinit(void)
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117 {
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118 outw(AUX_ENABLES, 1);
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119 outw(AUX_MU_CNTL_REG, 0);
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120 outw(AUX_MU_LCR_REG, 0x3);
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121 outw(AUX_MU_MCR_REG, 0);
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122 outw(AUX_MU_IER_REG, 0x1);
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123 outw(AUX_MU_IIR_REG, 0xC7);
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124 outw(AUX_MU_BAUD_REG, 270); // (250,000,000/(115200*8))-1 = 270
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125
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126 setgpiofunc(14, 2); // gpio 14, alt 5
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127 setgpiofunc(15, 2); // gpio 15, alt 5
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128
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129 outw(GPPUD, 0);
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130 delay(10);
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131 outw(GPPUDCLK0, (1 << 14) | (1 << 15) );
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132 delay(10);
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133 outw(GPPUDCLK0, 0);
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134
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135 outw(AUX_MU_CNTL_REG, 3);
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136 enableirqminiuart();
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137 }
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