#include <efi.h>
#include <efilib.h>

#include "elilo.h"
#include "pgtable_flags.h"
#include "sysdeps.h"
#include "registers.h"


#define ALIGN_4K 12 /* use 4KB aligned */

#define MEMCPY(to, from, cnt) { \
        UINT8 *t = (UINT8 *)(to); \
        UINT8 *f = (UINT8 *)(from); \
        UINTN n = cnt; \
        if (t && f && n && (t<f)) { \
                    while (n--) { \
                                    *t++ = *f++; \
                                } \
                } else if (t && f && n && (t>f)) { \
                            t += n; \
                            f += n; \
                            while (n--) { \
                                            *t-- = *f--; \
                                        } \
                        } \
}

#define MEMSET(ptr, size, val) { \
        UINT8 *p = (UINT8 *)(ptr); \
        UINTN n = (UINTN)(size); \
        UINT8 v = (UINT8)(val); \
        if (p && n) { \
                    while (n--) { \
                                    *p++ = v; \
                                } \
                } \
}


#define EFER_LME 8
#define EFER_NXE 0x00000400
#define MSR_EFER 0xc0000080

/*
VOID
operate_efer()
{
    UINT32 msr_efer = MSR_EFER;
    UINT32 efer_flg = EFER_LME;
    asm volatile ("movl %0, %%ecx \n\t rdmsr \n\t btsl %1, %%eax\n\t wrmsr " :: "m"(msr_efer) ,"m"(efer_flg));
}
*/


extern pml4_t *pml4;
extern pdpte_t *pdpte;

INTN
enable_cr4_pae(cr4_t cr4)
{
    asm volatile("mov %%cr4,%0\n\t" : "=r" (cr4));
    cr4.pae = ENABLE;
    asm volatile("mov %0,%%cr4": : "r" (cr4));
    //asm volatile("movq %%rax, %%cr4"::"a"(cr4_flag));
    return 0;
}

UINTN
insert_addr_to_cr3(cr3_t cr3, UINT64 addr)
{
    // asm volatile ("movq %0, %%rax \n\tmovq %%rax, %%cr3" :: "m"(addr) );
    /* write cr3 */
    Print(L"Read cr3.\n");
    asm volatile("mov %%cr3,%0\n\t" : "=r" (cr3));
    Print(L"Getting cr3 is pwt:%d, pcd:%d pdb 0x%lx\n addr:%lx \n", cr3.pwt, cr3.pcd, cr3.pdb, addr);
    addr = addr >> ALIGN_4K;
    cr3.pdb = addr;
    Print(L"Write addr:%lx to cr3 / cr3.pdb: %lx.\n", addr, cr3.pdb);
    asm volatile("mov %0,%%cr3": : "r" (cr3));
    Print(L"Written cr3.\n");
    return 0;
}

INTN
enable_paging_cr0(cr0_t cr0)
{   
    asm volatile("mov %%cr0,%0\n\t" : "=r" (cr0));
    cr0.pg = ENABLE;
    asm volatile("mov %0,%%cr0": : "r" (cr0));
    // asm volatile("movl %0, %%eax \n\t movq %%rax, %%cr0"::"m"(cr0_flag));
    return 0;
}

VOID
init_pgtable_value(VOID *addr, UINT32 size, UINT64 value)
{
    if (addr == NULL) {
        Print(L"addr is not using.\n");
        return;
    }

    UINT64 *tmp = (UINT64 *)addr;

    while(size--) {
        *tmp++ = value;
    }
}

#define PML4_START 0x00270000
#define PDPTE_START PML4_START + PML4_SIZE

/* alloc pages use how many pages for 4KiB */
#define PGCNT_BYTE 4096

/* PDPTE indicate original page is 1GB */
#define ORIG_PAGE_SIZE 1048576 


/* init_pgtable()
 * init pagetable. use IA-32e page table 
 * This function initialize PML4 and PDPTE 
 */
UINT64
init_pgtable()
{
    pml4 = (pml4_t *)PML4_START;
    UINTN pml4_size = PML4_SIZE * sizeof(pml4_t) / PGCNT_BYTE;
    Print(L"allocate pml4 ::%lx \n", pml4);
    pml4 = (pml4_t *)alloc_pages(pml4_size, EfiLoaderData, AllocateAddress, pml4);
    Print(L"pml4 :%lx\n", pml4);
    if (pml4 == NULL) {
        Print(L"can not allocate pml4.\n");
        return -1;
    }

    pdpte = (pdpte_t *)PDPTE_START;
    Print(L"allocate pdpte ::%lx\n", pdpte);
    UINTN pdpte_size = PDPTE_SIZE * PML4_SIZE * sizeof(pdpte_t) / PGCNT_BYTE;
    pdpte = (pdpte_t *)alloc_pages(pdpte_size , EfiLoaderData, AllocateAddress, pdpte);
    Print(L"pdpte :%lx\n", pdpte);

    if (pdpte == NULL) {
        Print(L"can not allocate pdpte.\n");
        return -1;
    }

    init_pgtable_value((VOID *)pml4, PML4_SIZE * sizeof(pml4_t), 0);
    init_pgtable_value((VOID *)pdpte, PDPTE_SIZE * PML4_SIZE * sizeof(pdpte_t), 0);

    UINT64 orig_addr_start = PDPTE_START + (PDPTE_SIZE * PML4_SIZE * sizeof(UINT64));
    UINTN i = 0;
    for (; i<PML4_SIZE ;i++) {
        UINT64 tmp_pdpte_addr = (UINT64)&pdpte[PDPTE_SIZE * i];
        tmp_pdpte_addr = tmp_pdpte_addr >> ALIGN_4K;
        pml4[i].paddr = tmp_pdpte_addr;
        pml4[i].p = ENABLE;
        UINTN j = 0;
        for (;j < PDPTE_SIZE; j++) {
            pdpte[(PDPTE_SIZE * i) + j].p = ENABLE;
            pdpte[(PDPTE_SIZE * i) + j].ps = ENABLE;
            pdpte[(PDPTE_SIZE * i) + j].paddr = orig_addr_start + (PDPTE_SIZE * i + j * ORIG_PAGE_SIZE) * sizeof(UINT64);
        }
    }

    return (UINT64)pml4;
}

VOID 
stop_kernel()
{
    Print(L"stop\n");
    while(1) {
    }
}

EFI_STATUS
start_elilo_kernel()
{
    cr0_t cr0;
    cr3_t cr3;
    cr4_t cr4;

    MEMSET(&cr0, sizeof(UINT64), 0);
    MEMSET(&cr3, sizeof(UINT64), 0);
    MEMSET(&cr4, sizeof(UINT64), 0);

    asm volatile ("cli"::);

    MEMSET(gdt_addr.base, gdt_addr.limit, 0);
    MEMCPY(gdt_addr.base, init_gdt, sizeof_init_gdt);

    // asm volatile ( "lidt %0" : : "m" (idt_addr) );
    // asm volatile ( "lgdt %0" : : "m" (gdt_addr) );

    Print(L"init pagetable...\n");
    UINT64 addr = init_pgtable();

    Print(L"enable cr4 pae...\n");
    enable_cr4_pae(cr4); 

    Print(L"enable paging cr0...\n");
    enable_paging_cr0(cr0);

    Print(L"insert addr %lx to cr3...\n", addr);
    insert_addr_to_cr3(cr3, addr);

    while(1) { }

    Print(L"finish to initialize...\n");

    asm volatile ("hlt" : : );
    Print(L"finish internal kernel\n");
    return EFI_SUCCESS;
}