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annotate lib/Target/PowerPC/PPCSubtarget.h @ 124:4fa72497ed5d

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fix
author mir3636
date Thu, 30 Nov 2017 20:04:56 +0900
parents 803732b1fca8
children
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1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
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15 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
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16
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17 #include "PPCFrameLowering.h"
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18 #include "PPCISelLowering.h"
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19 #include "PPCInstrInfo.h"
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20 #include "llvm/ADT/Triple.h"
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21 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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22 #include "llvm/IR/DataLayout.h"
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23 #include "llvm/MC/MCInstrItineraries.h"
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24 #include "llvm/Target/TargetSubtargetInfo.h"
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25 #include <string>
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26
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27 #define GET_SUBTARGETINFO_HEADER
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28 #include "PPCGenSubtargetInfo.inc"
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29
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30 // GCC #defines PPC on Linux but we use it as our namespace name
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31 #undef PPC
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32
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33 namespace llvm {
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34 class StringRef;
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35
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36 namespace PPC {
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37 // -m directive values.
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38 enum {
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39 DIR_NONE,
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40 DIR_32,
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41 DIR_440,
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42 DIR_601,
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43 DIR_602,
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44 DIR_603,
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45 DIR_7400,
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46 DIR_750,
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47 DIR_970,
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48 DIR_A2,
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49 DIR_E500mc,
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50 DIR_E5500,
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51 DIR_PWR3,
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52 DIR_PWR4,
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53 DIR_PWR5,
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54 DIR_PWR5X,
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55 DIR_PWR6,
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56 DIR_PWR6X,
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57 DIR_PWR7,
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58 DIR_PWR8,
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59 DIR_PWR9,
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60 DIR_64
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61 };
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62 }
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63
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64 class GlobalValue;
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65 class TargetMachine;
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66
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67 class PPCSubtarget : public PPCGenSubtargetInfo {
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68 public:
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69 enum POPCNTDKind {
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70 POPCNTD_Unavailable,
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71 POPCNTD_Slow,
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72 POPCNTD_Fast
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73 };
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74
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75 protected:
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76 /// TargetTriple - What processor and OS we're targeting.
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77 Triple TargetTriple;
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78
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79 /// stackAlignment - The minimum alignment known to hold of the stack frame on
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80 /// entry to the function and which must be maintained by every function.
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81 unsigned StackAlignment;
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82
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83 /// Selected instruction itineraries (one entry per itinerary class.)
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84 InstrItineraryData InstrItins;
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85
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86 /// Which cpu directive was used.
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87 unsigned DarwinDirective;
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88
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89 /// Used by the ISel to turn in optimizations for POWER4-derived architectures
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90 bool HasMFOCRF;
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91 bool Has64BitSupport;
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92 bool Use64BitRegs;
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93 bool UseCRBits;
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94 bool HasHardFloat;
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95 bool IsPPC64;
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96 bool HasAltivec;
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97 bool HasSPE;
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98 bool HasQPX;
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99 bool HasVSX;
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100 bool HasP8Vector;
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101 bool HasP8Altivec;
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102 bool HasP8Crypto;
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103 bool HasP9Vector;
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104 bool HasP9Altivec;
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105 bool HasFCPSGN;
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106 bool HasFSQRT;
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107 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
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108 bool HasRecipPrec;
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109 bool HasSTFIWX;
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110 bool HasLFIWAX;
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111 bool HasFPRND;
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112 bool HasFPCVT;
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113 bool HasISEL;
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114 bool HasBPERMD;
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115 bool HasExtDiv;
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116 bool HasCMPB;
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117 bool HasLDBRX;
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118 bool IsBookE;
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119 bool HasOnlyMSYNC;
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120 bool IsE500;
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121 bool IsPPC4xx;
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122 bool IsPPC6xx;
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123 bool FeatureMFTB;
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124 bool DeprecatedDST;
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125 bool HasLazyResolverStubs;
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126 bool IsLittleEndian;
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127 bool HasICBT;
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128 bool HasInvariantFunctionDescriptors;
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129 bool HasPartwordAtomics;
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130 bool HasDirectMove;
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131 bool HasHTM;
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132 bool HasFusion;
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133 bool HasFloat128;
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134 bool IsISA3_0;
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135 bool UseLongCalls;
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136
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137 POPCNTDKind HasPOPCNTD;
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139 /// When targeting QPX running a stock PPC64 Linux kernel where the stack
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140 /// alignment has not been changed, we need to keep the 16-byte alignment
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141 /// of the stack.
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142 bool IsQPXStackUnaligned;
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143
83
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144 const PPCTargetMachine &TM;
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145 PPCFrameLowering FrameLowering;
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146 PPCInstrInfo InstrInfo;
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147 PPCTargetLowering TLInfo;
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148 SelectionDAGTargetInfo TSInfo;
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149
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150 public:
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151 /// This constructor initializes the data members to match that
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152 /// of the specified triple.
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153 ///
95
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154 PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
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155 const PPCTargetMachine &TM);
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156
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157 /// ParseSubtargetFeatures - Parses features string setting specified
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158 /// subtarget options. Definition of function is auto generated by tblgen.
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159 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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160
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161 /// getStackAlignment - Returns the minimum alignment known to hold of the
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162 /// stack frame on entry to the function and which must be maintained by every
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163 /// function for this subtarget.
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164 unsigned getStackAlignment() const { return StackAlignment; }
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165
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166 /// getDarwinDirective - Returns the -m directive specified for the cpu.
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167 ///
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168 unsigned getDarwinDirective() const { return DarwinDirective; }
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169
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170 /// getInstrItins - Return the instruction itineraries based on subtarget
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171 /// selection.
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172 const InstrItineraryData *getInstrItineraryData() const override {
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173 return &InstrItins;
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174 }
0
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175
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176 const PPCFrameLowering *getFrameLowering() const override {
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177 return &FrameLowering;
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178 }
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179 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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180 const PPCTargetLowering *getTargetLowering() const override {
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181 return &TLInfo;
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182 }
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183 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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184 return &TSInfo;
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185 }
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186 const PPCRegisterInfo *getRegisterInfo() const override {
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187 return &getInstrInfo()->getRegisterInfo();
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188 }
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189 const PPCTargetMachine &getTargetMachine() const { return TM; }
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190
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191 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
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192 /// so that we can use initializer lists for subtarget initialization.
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193 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
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194
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195 private:
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196 void initializeEnvironment();
77
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197 void initSubtargetFeatures(StringRef CPU, StringRef FS);
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198
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199 public:
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200 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
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201 ///
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202 bool isPPC64() const;
0
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203
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204 /// has64BitSupport - Return true if the selected CPU supports 64-bit
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205 /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
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206 bool has64BitSupport() const { return Has64BitSupport; }
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207 // useSoftFloat - Return true if soft-float option is turned on.
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208 bool useSoftFloat() const { return !HasHardFloat; }
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209
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210 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
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211 /// registers in 32-bit mode when possible. This can only true if
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212 /// has64BitSupport() returns true.
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213 bool use64BitRegs() const { return Use64BitRegs; }
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214
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215 /// useCRBits - Return true if we should store and manipulate i1 values in
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216 /// the individual condition register bits.
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217 bool useCRBits() const { return UseCRBits; }
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218
0
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219 /// hasLazyResolverStub - Return true if accesses to the specified global have
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220 /// to go through a dyld lazy resolution stub. This means that an extra load
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221 /// is required to get the address of the global.
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222 bool hasLazyResolverStub(const GlobalValue *GV) const;
0
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223
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224 // isLittleEndian - True if generating little-endian code
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225 bool isLittleEndian() const { return IsLittleEndian; }
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226
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227 // Specific obvious features.
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228 bool hasFCPSGN() const { return HasFCPSGN; }
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229 bool hasFSQRT() const { return HasFSQRT; }
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230 bool hasFRE() const { return HasFRE; }
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231 bool hasFRES() const { return HasFRES; }
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232 bool hasFRSQRTE() const { return HasFRSQRTE; }
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233 bool hasFRSQRTES() const { return HasFRSQRTES; }
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234 bool hasRecipPrec() const { return HasRecipPrec; }
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235 bool hasSTFIWX() const { return HasSTFIWX; }
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236 bool hasLFIWAX() const { return HasLFIWAX; }
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237 bool hasFPRND() const { return HasFPRND; }
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238 bool hasFPCVT() const { return HasFPCVT; }
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239 bool hasAltivec() const { return HasAltivec; }
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240 bool hasSPE() const { return HasSPE; }
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241 bool hasQPX() const { return HasQPX; }
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242 bool hasVSX() const { return HasVSX; }
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243 bool hasP8Vector() const { return HasP8Vector; }
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244 bool hasP8Altivec() const { return HasP8Altivec; }
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245 bool hasP8Crypto() const { return HasP8Crypto; }
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246 bool hasP9Vector() const { return HasP9Vector; }
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247 bool hasP9Altivec() const { return HasP9Altivec; }
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248 bool hasMFOCRF() const { return HasMFOCRF; }
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249 bool hasISEL() const { return HasISEL; }
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250 bool hasBPERMD() const { return HasBPERMD; }
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251 bool hasExtDiv() const { return HasExtDiv; }
83
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252 bool hasCMPB() const { return HasCMPB; }
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253 bool hasLDBRX() const { return HasLDBRX; }
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254 bool isBookE() const { return IsBookE; }
83
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255 bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
77
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diff changeset
256 bool isPPC4xx() const { return IsPPC4xx; }
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257 bool isPPC6xx() const { return IsPPC6xx; }
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258 bool isE500() const { return IsE500; }
95
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diff changeset
259 bool isFeatureMFTB() const { return FeatureMFTB; }
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260 bool isDeprecatedDST() const { return DeprecatedDST; }
83
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diff changeset
261 bool hasICBT() const { return HasICBT; }
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diff changeset
262 bool hasInvariantFunctionDescriptors() const {
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263 return HasInvariantFunctionDescriptors;
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264 }
95
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diff changeset
265 bool hasPartwordAtomics() const { return HasPartwordAtomics; }
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diff changeset
266 bool hasDirectMove() const { return HasDirectMove; }
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diff changeset
267
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268 bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
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269 unsigned getPlatformStackAlignment() const {
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270 if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
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271 return 32;
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272
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273 return 16;
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274 }
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275
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276 // DarwinABI has a 224-byte red zone. PPC32 SVR4ABI(Non-DarwinABI) has no
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277 // red zone and PPC64 SVR4ABI has a 288-byte red zone.
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278 unsigned getRedZoneSize() const {
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279 return isDarwinABI() ? 224 : (isPPC64() ? 288 : 0);
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280 }
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281
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282 bool hasHTM() const { return HasHTM; }
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283 bool hasFusion() const { return HasFusion; }
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284 bool hasFloat128() const { return HasFloat128; }
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285 bool isISA3_0() const { return IsISA3_0; }
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286 bool useLongCalls() const { return UseLongCalls; }
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287 bool needsSwapsForVSXMemOps() const {
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288 return hasVSX() && isLittleEndian() && !hasP9Vector();
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289 }
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290
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291 POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
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292
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293 const Triple &getTargetTriple() const { return TargetTriple; }
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294
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295 /// isDarwin - True if this is any darwin platform.
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296 bool isDarwin() const { return TargetTriple.isMacOSX(); }
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297 /// isBGQ - True if this is a BG/Q platform.
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298 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
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299
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300 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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301 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
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302 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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303
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304 bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
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305 bool isSVR4ABI() const { return !isDarwinABI(); }
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306 bool isELFv2ABI() const;
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307
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308 /// Originally, this function return hasISEL(). Now we always enable it,
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309 /// but may expand the ISEL instruction later.
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310 bool enableEarlyIfConversion() const override { return true; }
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311
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312 // Scheduling customization.
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313 bool enableMachineScheduler() const override;
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314 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
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315 bool enablePostRAScheduler() const override;
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316 AntiDepBreakMode getAntiDepBreakMode() const override;
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317 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
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318
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319 void overrideSchedPolicy(MachineSchedPolicy &Policy,
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320 unsigned NumRegionInstrs) const override;
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321 bool useAA() const override;
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322
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323 bool enableSubRegLiveness() const override;
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324
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325 /// classifyGlobalReference - Classify a global variable reference for the
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326 /// current subtarget accourding to how we should reference it.
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327 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
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328
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329 bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
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330 };
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331 } // End llvm namespace
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332
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333 #endif