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annotate docs/HistoricalNotes/2001-06-01-GCCOptimizations2.txt @ 83:60c9769439b8

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 95c75e76d11b
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 Date: Fri, 1 Jun 2001 17:08:44 -0500 (CDT)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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2 From: Chris Lattner <sabre@nondot.org>
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3 To: Vikram S. Adve <vadve@cs.uiuc.edu>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 Subject: RE: Interesting: GCC passes
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5
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6 > That is very interesting. I agree that some of these could be done on LLVM
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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7 > at link-time, but it is the extra time required that concerns me. Link-time
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8 > optimization is severely time-constrained.
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9
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10 If we were to reimplement any of these optimizations, I assume that we
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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11 could do them a translation unit at a time, just as GCC does now. This
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 would lead to a pipeline like this:
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13
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14 Static optimizations, xlation unit at a time:
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15 .c --GCC--> .llvm --llvmopt--> .llvm
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16
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17 Link time optimizations:
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18 .llvm --llvm-ld--> .llvm --llvm-link-opt--> .llvm
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19
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20 Of course, many optimizations could be shared between llvmopt and
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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21 llvm-link-opt, but the wouldn't need to be shared... Thus compile time
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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22 could be faster, because we are using a "smarter" IR (SSA based).
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23
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24 > BTW, about SGI, "borrowing" SSA-based optimizations from one compiler and
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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25 > putting it into another is not necessarily easier than re-doing it.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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26 > Optimization code is usually heavily tied in to the specific IR they use.
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27
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28 Understood. The only reason that I brought this up is because SGI's IR is
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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29 more similar to LLVM than it is different in many respects (SSA based,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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30 relatively low level, etc), and could be easily adapted. Also their
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31 optimizations are written in C++ and are actually somewhat
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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32 structured... of course it would be no walk in the park, but it would be
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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33 much less time consuming to adapt, say, SSA-PRE than to rewrite it.
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34
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35 > But your larger point is valid that adding SSA based optimizations is
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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36 > feasible and should be fun. (Again, link time cost is the issue.)
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37
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38 Assuming linktime cost wasn't an issue, the question is:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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39 Does using GCC's backend buy us anything?
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40
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41 > It also occurs to me that GCC is probably doing quite a bit of back-end
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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42 > optimization (step 16 in your list). Do you have a breakdown of that?
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43
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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44 Not really. The irritating part of GCC is that it mixes it all up and
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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45 doesn't have a clean separation of concerns. A lot of the "back end
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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46 optimization" happens right along with other data optimizations (ie, CSE
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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47 of machine specific things).
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48
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49 As far as REAL back end optimizations go, it looks something like this:
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50
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51 1. Instruction combination: try to make CISCy instructions, if available
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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52 2. Register movement: try to get registers in the right places for the
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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53 architecture to avoid register to register moves. For example, try to get
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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54 the first argument of a function to naturally land in %o0 for sparc.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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55 3. Instruction scheduling: 'nuff said :)
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56 4. Register class preferencing: ??
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57 5. Local register allocation
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58 6. global register allocation
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59 7. Spilling
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60 8. Local regalloc
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61 9. Jump optimization
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62 10. Delay slot scheduling
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63 11. Branch shorting for CISC machines
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64 12. Instruction selection & peephole optimization
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65 13. Debug info output
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66
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67 But none of this would be usable for LLVM anyways, unless we were using
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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68 GCC as a static compiler.
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69
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70 -Chris
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71