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1 //=- X86ScheduleBtVer2.td - X86 BtVer2 (Jaguar) Scheduling ---*- tablegen -*-=//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the machine model for AMD btver2 (Jaguar) to support
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11 // instruction scheduling and other instruction cost heuristics. Based off AMD Software
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12 // Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix.
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13 //
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14 //===----------------------------------------------------------------------===//
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15
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16 def BtVer2Model : SchedMachineModel {
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17 // All x86 instructions are modeled as a single micro-op, and btver2 can
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18 // decode 2 instructions per cycle.
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19 let IssueWidth = 2;
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20 let MicroOpBufferSize = 64; // Retire Control Unit
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21 let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency)
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22 let HighLatency = 25;
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23 let MispredictPenalty = 14; // Minimum branch misdirection penalty
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24 let PostRAScheduler = 1;
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25
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26 // FIXME: SSE4/AVX is unimplemented. This flag is set to allow
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27 // the scheduler to assign a default model to unrecognized opcodes.
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28 let CompleteModel = 0;
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29 }
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30
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31 let SchedModel = BtVer2Model in {
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32
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33 // Jaguar can issue up to 6 micro-ops in one cycle
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34 def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam)
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35 def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV
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36 def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU
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37 def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA)
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38 def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
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39 def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
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40
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41 // Any pipe - FIXME we need this until we can discriminate between int/fpu load/store/moves properly
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42 def JAny : ProcResGroup<[JALU0, JALU1, JLAGU, JSAGU, JFPU0, JFPU1]>;
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43
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44 // Integer Pipe Scheduler
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45 def JALU01 : ProcResGroup<[JALU0, JALU1]> {
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46 let BufferSize=20;
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47 }
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48
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49 // AGU Pipe Scheduler
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50 def JLSAGU : ProcResGroup<[JLAGU, JSAGU]> {
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51 let BufferSize=12;
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52 }
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53
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54 // Fpu Pipe Scheduler
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55 def JFPU01 : ProcResGroup<[JFPU0, JFPU1]> {
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56 let BufferSize=18;
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57 }
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58
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59 def JDiv : ProcResource<1>; // integer division
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60 def JMul : ProcResource<1>; // integer multiplication
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61 def JVALU0 : ProcResource<1>; // vector integer
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62 def JVALU1 : ProcResource<1>; // vector integer
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63 def JVIMUL : ProcResource<1>; // vector integer multiplication
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64 def JSTC : ProcResource<1>; // vector store/convert
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65 def JFPM : ProcResource<1>; // FP multiplication
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66 def JFPA : ProcResource<1>; // FP addition
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67
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68 // Integer loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
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69 // cycles after the memory operand.
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70 def : ReadAdvance<ReadAfterLd, 3>;
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71
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72 // Many SchedWrites are defined in pairs with and without a folded load.
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73 // Instructions with folded loads are usually micro-fused, so they only appear
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74 // as two micro-ops when dispatched by the schedulers.
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75 // This multiclass defines the resource usage for variants with and without
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76 // folded loads.
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77 multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
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78 ProcResourceKind ExePort,
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79 int Lat> {
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80 // Register variant is using a single cycle on ExePort.
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81 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
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82
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83 // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
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84 // latency.
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85 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
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86 let Latency = !add(Lat, 3);
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87 }
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88 }
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89
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90 multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
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91 ProcResourceKind ExePort,
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92 int Lat> {
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93 // Register variant is using a single cycle on ExePort.
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94 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
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95
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96 // Memory variant also uses a cycle on JLAGU and adds 5 cycles to the
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97 // latency.
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98 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
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99 let Latency = !add(Lat, 5);
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100 }
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101 }
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102
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103 // A folded store needs a cycle on the SAGU for the store data.
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104 def : WriteRes<WriteRMW, [JSAGU]>;
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105
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106 ////////////////////////////////////////////////////////////////////////////////
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107 // Arithmetic.
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108 ////////////////////////////////////////////////////////////////////////////////
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109
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110 defm : JWriteResIntPair<WriteALU, JALU01, 1>;
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111 defm : JWriteResIntPair<WriteIMul, JALU1, 3>;
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112
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113 def : WriteRes<WriteIMulH, [JALU1]> {
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114 let Latency = 6;
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115 let ResourceCycles = [4];
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116 }
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117
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118 // FIXME 8/16 bit divisions
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119 def : WriteRes<WriteIDiv, [JALU1, JDiv]> {
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120 let Latency = 25;
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121 let ResourceCycles = [1, 25];
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122 }
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123 def : WriteRes<WriteIDivLd, [JALU1, JLAGU, JDiv]> {
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124 let Latency = 41;
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125 let ResourceCycles = [1, 1, 25];
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126 }
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127
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128 // This is for simple LEAs with one or two input operands.
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129 // FIXME: SAGU 3-operand LEA
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130 def : WriteRes<WriteLEA, [JALU01]>;
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131
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132 ////////////////////////////////////////////////////////////////////////////////
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133 // Integer shifts and rotates.
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134 ////////////////////////////////////////////////////////////////////////////////
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135
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136 defm : JWriteResIntPair<WriteShift, JALU01, 1>;
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137
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138 ////////////////////////////////////////////////////////////////////////////////
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139 // Loads, stores, and moves, not folded with other operations.
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140 // FIXME: Split x86 and SSE load/store/moves
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141 ////////////////////////////////////////////////////////////////////////////////
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142
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143 def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; }
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144 def : WriteRes<WriteStore, [JSAGU]>;
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145 def : WriteRes<WriteMove, [JAny]>;
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146
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147 ////////////////////////////////////////////////////////////////////////////////
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148 // Idioms that clear a register, like xorps %xmm0, %xmm0.
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149 // These can often bypass execution ports completely.
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150 ////////////////////////////////////////////////////////////////////////////////
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151
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152 def : WriteRes<WriteZero, []>;
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153
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154 ////////////////////////////////////////////////////////////////////////////////
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155 // Branches don't produce values, so they have no latency, but they still
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156 // consume resources. Indirect branches can fold loads.
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157 ////////////////////////////////////////////////////////////////////////////////
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158
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159 defm : JWriteResIntPair<WriteJump, JALU01, 1>;
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160
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161 ////////////////////////////////////////////////////////////////////////////////
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162 // Floating point. This covers both scalar and vector operations.
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163 // FIXME: should we bother splitting JFPU pipe + unit stages for fast instructions?
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164 // FIXME: Double precision latencies
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165 // FIXME: SS vs PS latencies
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166 // FIXME: ymm latencies
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167 ////////////////////////////////////////////////////////////////////////////////
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168
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169 defm : JWriteResFpuPair<WriteFAdd, JFPU0, 3>;
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170 defm : JWriteResFpuPair<WriteFMul, JFPU1, 2>;
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171 defm : JWriteResFpuPair<WriteFRcp, JFPU1, 2>;
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172 defm : JWriteResFpuPair<WriteFRsqrt, JFPU1, 2>;
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173 defm : JWriteResFpuPair<WriteFShuffle, JFPU01, 1>;
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174 defm : JWriteResFpuPair<WriteFBlend, JFPU01, 1>;
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175 defm : JWriteResFpuPair<WriteFShuffle256, JFPU01, 1>;
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176
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177 def : WriteRes<WriteFSqrt, [JFPU1, JLAGU, JFPM]> {
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178 let Latency = 21;
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179 let ResourceCycles = [1, 1, 21];
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180 }
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181 def : WriteRes<WriteFSqrtLd, [JFPU1, JLAGU, JFPM]> {
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182 let Latency = 26;
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183 let ResourceCycles = [1, 1, 21];
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184 }
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185
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186 def : WriteRes<WriteFDiv, [JFPU1, JLAGU, JFPM]> {
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187 let Latency = 19;
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188 let ResourceCycles = [1, 1, 19];
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189 }
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190 def : WriteRes<WriteFDivLd, [JFPU1, JLAGU, JFPM]> {
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191 let Latency = 24;
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192 let ResourceCycles = [1, 1, 19];
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193 }
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194
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195 // FIXME: integer pipes
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196 defm : JWriteResFpuPair<WriteCvtF2I, JFPU1, 3>; // Float -> Integer.
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197 defm : JWriteResFpuPair<WriteCvtI2F, JFPU1, 3>; // Integer -> Float.
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198 defm : JWriteResFpuPair<WriteCvtF2F, JFPU1, 3>; // Float -> Float size conversion.
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199
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200 def : WriteRes<WriteFVarBlend, [JFPU01]> {
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201 let Latency = 2;
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202 let ResourceCycles = [2];
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203 }
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204 def : WriteRes<WriteFVarBlendLd, [JLAGU, JFPU01]> {
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205 let Latency = 7;
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206 let ResourceCycles = [1, 2];
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207 }
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208
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209 // Vector integer operations.
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210 defm : JWriteResFpuPair<WriteVecALU, JFPU01, 1>;
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211 defm : JWriteResFpuPair<WriteVecShift, JFPU01, 1>;
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212 defm : JWriteResFpuPair<WriteVecIMul, JFPU0, 2>;
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213 defm : JWriteResFpuPair<WriteShuffle, JFPU01, 1>;
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214 defm : JWriteResFpuPair<WriteBlend, JFPU01, 1>;
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215 defm : JWriteResFpuPair<WriteVecLogic, JFPU01, 1>;
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216 defm : JWriteResFpuPair<WriteShuffle256, JFPU01, 1>;
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217
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218 def : WriteRes<WriteVarBlend, [JFPU01]> {
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219 let Latency = 2;
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220 let ResourceCycles = [2];
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221 }
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222 def : WriteRes<WriteVarBlendLd, [JLAGU, JFPU01]> {
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223 let Latency = 7;
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224 let ResourceCycles = [1, 2];
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225 }
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226
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227 // FIXME: why do we need to define AVX2 resource on CPU that doesn't have AVX2?
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228 def : WriteRes<WriteVarVecShift, [JFPU01]> {
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229 let Latency = 1;
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230 let ResourceCycles = [1];
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231 }
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232 def : WriteRes<WriteVarVecShiftLd, [JLAGU, JFPU01]> {
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233 let Latency = 6;
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234 let ResourceCycles = [1, 1];
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235 }
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236
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237 def : WriteRes<WriteMPSAD, [JFPU0]> {
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238 let Latency = 3;
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239 let ResourceCycles = [2];
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240 }
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241 def : WriteRes<WriteMPSADLd, [JLAGU, JFPU0]> {
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242 let Latency = 8;
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243 let ResourceCycles = [1, 2];
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244 }
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245
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246 ////////////////////////////////////////////////////////////////////////////////
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247 // String instructions.
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248 // Packed Compare Implicit Length Strings, Return Mask
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249 // FIXME: approximate latencies + pipe dependencies
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250 ////////////////////////////////////////////////////////////////////////////////
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251
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252 def : WriteRes<WritePCmpIStrM, [JFPU01]> {
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253 let Latency = 7;
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254 let ResourceCycles = [2];
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255 }
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256 def : WriteRes<WritePCmpIStrMLd, [JLAGU, JFPU01]> {
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257 let Latency = 12;
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258 let ResourceCycles = [1, 2];
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259 }
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260
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261 // Packed Compare Explicit Length Strings, Return Mask
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262 def : WriteRes<WritePCmpEStrM, [JFPU01]> {
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263 let Latency = 13;
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264 let ResourceCycles = [5];
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265 }
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266 def : WriteRes<WritePCmpEStrMLd, [JLAGU, JFPU01]> {
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267 let Latency = 18;
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268 let ResourceCycles = [1, 5];
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269 }
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270
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271 // Packed Compare Implicit Length Strings, Return Index
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272 def : WriteRes<WritePCmpIStrI, [JFPU01]> {
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273 let Latency = 6;
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274 let ResourceCycles = [2];
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275 }
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276 def : WriteRes<WritePCmpIStrILd, [JLAGU, JFPU01]> {
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277 let Latency = 11;
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278 let ResourceCycles = [1, 2];
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279 }
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280
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281 // Packed Compare Explicit Length Strings, Return Index
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282 def : WriteRes<WritePCmpEStrI, [JFPU01]> {
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283 let Latency = 13;
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284 let ResourceCycles = [5];
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285 }
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286 def : WriteRes<WritePCmpEStrILd, [JLAGU, JFPU01]> {
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287 let Latency = 18;
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288 let ResourceCycles = [1, 5];
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289 }
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290
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291 ////////////////////////////////////////////////////////////////////////////////
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292 // AES Instructions.
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293 ////////////////////////////////////////////////////////////////////////////////
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294
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295 def : WriteRes<WriteAESDecEnc, [JFPU01, JVIMUL]> {
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296 let Latency = 3;
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297 let ResourceCycles = [1, 1];
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298 }
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299 def : WriteRes<WriteAESDecEncLd, [JFPU01, JLAGU, JVIMUL]> {
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300 let Latency = 8;
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301 let ResourceCycles = [1, 1, 1];
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302 }
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303
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304 def : WriteRes<WriteAESIMC, [JVIMUL]> {
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305 let Latency = 2;
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306 let ResourceCycles = [1];
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307 }
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308 def : WriteRes<WriteAESIMCLd, [JLAGU, JVIMUL]> {
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309 let Latency = 7;
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310 let ResourceCycles = [1, 1];
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311 }
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312
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313 def : WriteRes<WriteAESKeyGen, [JVIMUL]> {
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314 let Latency = 2;
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315 let ResourceCycles = [1];
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316 }
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317 def : WriteRes<WriteAESKeyGenLd, [JLAGU, JVIMUL]> {
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318 let Latency = 7;
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319 let ResourceCycles = [1, 1];
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320 }
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321
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322 ////////////////////////////////////////////////////////////////////////////////
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323 // Carry-less multiplication instructions.
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324 ////////////////////////////////////////////////////////////////////////////////
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325
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326 def : WriteRes<WriteCLMul, [JVIMUL]> {
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327 let Latency = 2;
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328 let ResourceCycles = [1];
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329 }
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330 def : WriteRes<WriteCLMulLd, [JLAGU, JVIMUL]> {
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331 let Latency = 7;
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332 let ResourceCycles = [1, 1];
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333 }
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334
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335 // FIXME: pipe for system/microcode?
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336 def : WriteRes<WriteSystem, [JAny]> { let Latency = 100; }
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337 def : WriteRes<WriteMicrocoded, [JAny]> { let Latency = 100; }
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338 def : WriteRes<WriteFence, [JSAGU]>;
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339 def : WriteRes<WriteNop, []>;
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340 } // SchedModel
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341
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