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1 //===-- PPCScheduleP8.td - PPC P8 Scheduling Definitions ---*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the itinerary class data for the POWER8 processor.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 // Scheduling for the P8 involves tracking two types of resources:
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15 // 1. The dispatch bundle slots
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16 // 2. The functional unit resources
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17
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18 // Dispatch units:
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19 def P8_DU1 : FuncUnit;
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20 def P8_DU2 : FuncUnit;
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21 def P8_DU3 : FuncUnit;
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22 def P8_DU4 : FuncUnit;
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23 def P8_DU5 : FuncUnit;
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24 def P8_DU6 : FuncUnit;
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25 def P8_DU7 : FuncUnit; // Only branch instructions will use DU7,DU8
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26 def P8_DU8 : FuncUnit;
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27
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28 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
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29
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30 def P8_LU1 : FuncUnit; // Loads or fixed-point operations 1
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31 def P8_LU2 : FuncUnit; // Loads or fixed-point operations 2
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32
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33 // Load/Store pipelines can handle Stores, fixed-point loads, and simple
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34 // fixed-point operations.
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35 def P8_LSU1 : FuncUnit; // Load/Store pipeline 1
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36 def P8_LSU2 : FuncUnit; // Load/Store pipeline 2
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37
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38 // Fixed Point unit
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39 def P8_FXU1 : FuncUnit; // FX pipeline 1
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40 def P8_FXU2 : FuncUnit; // FX pipeline 2
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41
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42 // The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
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43 // are combined on P7 and newer into a Vector Scalar Unit (VSU).
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44 // The P8 Instruction latency documents still refers to the unit as the
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45 // FPU, so keep in mind that FPU==VSU.
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46 // In contrast to the P7, the VMX units on P8 are symmetric, so no need to
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47 // split vector integer ops or 128-bit load/store/perms to the specific units.
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48 def P8_FPU1 : FuncUnit; // VS pipeline 1
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49 def P8_FPU2 : FuncUnit; // VS pipeline 2
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50
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51 def P8_CRU : FuncUnit; // CR unit (CR logicals and move-from-SPRs)
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52 def P8_BRU : FuncUnit; // BR unit
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53
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54 def P8Itineraries : ProcessorItineraries<
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55 [P8_DU1, P8_DU2, P8_DU3, P8_DU4, P8_DU5, P8_DU6, P8_DU7, P8_DU8,
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56 P8_LU1, P8_LU2, P8_LSU1, P8_LSU2, P8_FXU1, P8_FXU2,
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57 P8_FPU1, P8_FPU2, P8_CRU, P8_BRU], [], [
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58 InstrItinData<IIC_IntSimple , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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59 P8_DU4, P8_DU5, P8_DU6], 0>,
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60 InstrStage<1, [P8_FXU1, P8_FXU2,
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61 P8_LU1, P8_LU2,
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62 P8_LSU1, P8_LSU2]>],
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63 [1, 1, 1]>,
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64 InstrItinData<IIC_IntGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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65 P8_DU4, P8_DU5, P8_DU6], 0>,
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66 InstrStage<1, [P8_FXU1, P8_FXU2, P8_LU1,
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67 P8_LU2, P8_LSU1, P8_LSU2]>],
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68 [1, 1, 1]>,
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69 InstrItinData<IIC_IntISEL, [InstrStage<1, [P8_DU1], 0>,
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70 InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
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71 InstrStage<1, [P8_BRU]>],
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72 [1, 1, 1, 1]>,
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73 InstrItinData<IIC_IntCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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74 P8_DU4, P8_DU5, P8_DU6], 0>,
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75 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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76 [1, 1, 1]>,
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77 InstrItinData<IIC_IntDivW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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78 P8_DU4, P8_DU5, P8_DU6], 0>,
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79 InstrStage<15, [P8_FXU1, P8_FXU2]>],
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80 [15, 1, 1]>,
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81 InstrItinData<IIC_IntDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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82 P8_DU4, P8_DU5, P8_DU6], 0>,
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83 InstrStage<23, [P8_FXU1, P8_FXU2]>],
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84 [23, 1, 1]>,
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85 InstrItinData<IIC_IntMulHW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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86 P8_DU4, P8_DU5, P8_DU6], 0>,
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87 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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88 [4, 1, 1]>,
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89 InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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90 P8_DU4, P8_DU5, P8_DU6], 0>,
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91 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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92 [4, 1, 1]>,
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93 InstrItinData<IIC_IntMulLI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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94 P8_DU4, P8_DU5, P8_DU6], 0>,
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95 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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96 [4, 1, 1]>,
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97 InstrItinData<IIC_IntRotate , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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98 P8_DU4, P8_DU5, P8_DU6], 0>,
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99 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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100 [1, 1, 1]>,
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101 InstrItinData<IIC_IntRotateD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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102 P8_DU4, P8_DU5, P8_DU6], 0>,
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103 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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104 [1, 1, 1]>,
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105 InstrItinData<IIC_IntShift , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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106 P8_DU4, P8_DU5, P8_DU6], 0>,
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107 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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108 [1, 1, 1]>,
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109 InstrItinData<IIC_IntTrapW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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110 P8_DU4, P8_DU5, P8_DU6], 0>,
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111 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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112 [1, 1]>,
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113 InstrItinData<IIC_IntTrapD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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114 P8_DU4, P8_DU5, P8_DU6], 0>,
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115 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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116 [1, 1]>,
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117 InstrItinData<IIC_BrB , [InstrStage<1, [P8_DU7, P8_DU8], 0>,
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118 InstrStage<1, [P8_BRU]>],
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119 [3, 1, 1]>,
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120 // FIXME - the Br* groups below are not branch related, so should probably
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121 // be renamed.
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122 // IIC_BrCR consists of the cr* instructions. (crand,crnor,creqv, etc).
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123 // and should be 'First' in dispatch.
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124 InstrItinData<IIC_BrCR , [InstrStage<1, [P8_DU1], 0>,
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125 InstrStage<1, [P8_CRU]>],
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126 [3, 1, 1]>,
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127 // IIC_BrMCR consists of the mcrf instruction.
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128 InstrItinData<IIC_BrMCR , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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129 P8_DU4, P8_DU5, P8_DU6], 0>,
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130 InstrStage<1, [P8_CRU]>],
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131 [3, 1, 1]>,
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132 // IIC_BrMCRX consists of mcrxr (obsolete instruction) and mtcrf, which
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133 // should be first in the dispatch group.
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134 InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
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135 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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136 [3, 1, 1]>,
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137 InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
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138 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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139 [3, 1]>,
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140 InstrItinData<IIC_LdStLoad , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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141 P8_DU4, P8_DU5, P8_DU6], 0>,
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142 InstrStage<1, [P8_LSU1, P8_LSU2,
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143 P8_LU1, P8_LU2]>],
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144 [2, 1, 1]>,
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145 InstrItinData<IIC_LdStLoadUpd , [InstrStage<1, [P8_DU1], 0>,
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146 InstrStage<1, [P8_DU2], 0>,
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147 InstrStage<1, [P8_LSU1, P8_LSU2,
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148 P8_LU1, P8_LU2 ], 0>,
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149 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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150 [2, 2, 1, 1]>,
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151 // Update-Indexed form loads/stores are no longer first and last in the
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152 // dispatch group. They are simply cracked, so require DU1,DU2.
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153 InstrItinData<IIC_LdStLoadUpdX, [InstrStage<1, [P8_DU1], 0>,
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154 InstrStage<1, [P8_DU2], 0>,
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155 InstrStage<1, [P8_LSU1, P8_LSU2,
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156 P8_LU1, P8_LU2], 0>,
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157 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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158 [3, 3, 1, 1]>,
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159 InstrItinData<IIC_LdStLD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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160 P8_DU4, P8_DU5, P8_DU6], 0>,
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161 InstrStage<1, [P8_LSU1, P8_LSU2,
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162 P8_LU1, P8_LU2]>],
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163 [2, 1, 1]>,
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164 InstrItinData<IIC_LdStLDU , [InstrStage<1, [P8_DU1], 0>,
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165 InstrStage<1, [P8_DU2], 0>,
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166 InstrStage<1, [P8_LSU1, P8_LSU2,
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167 P8_LU1, P8_LU2], 0>,
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168 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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169 [2, 2, 1, 1]>,
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170 InstrItinData<IIC_LdStLDUX , [InstrStage<1, [P8_DU1], 0>,
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171 InstrStage<1, [P8_DU2], 0>,
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172 InstrStage<1, [P8_LSU1, P8_LSU2,
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173 P8_LU1, P8_LU2], 0>,
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174 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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175 [3, 3, 1, 1]>,
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176 InstrItinData<IIC_LdStLFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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177 P8_DU4, P8_DU5, P8_DU6], 0>,
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178 InstrStage<1, [P8_LU1, P8_LU2]>],
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179 [3, 1, 1]>,
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180 InstrItinData<IIC_LdStLVecX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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181 P8_DU4, P8_DU5, P8_DU6], 0>,
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182 InstrStage<1, [P8_LU1, P8_LU2]>],
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183 [3, 1, 1]>,
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184 InstrItinData<IIC_LdStLFDU , [InstrStage<1, [P8_DU1], 0>,
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185 InstrStage<1, [P8_DU2], 0>,
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186 InstrStage<1, [P8_LU1, P8_LU2], 0>,
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187 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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188 [3, 3, 1, 1]>,
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189 InstrItinData<IIC_LdStLFDUX , [InstrStage<1, [P8_DU1], 0>,
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190 InstrStage<1, [P8_DU2], 0>,
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191 InstrStage<1, [P8_LU1, P8_LU2], 0>,
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192 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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193 [3, 3, 1, 1]>,
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194 InstrItinData<IIC_LdStLHA , [InstrStage<1, [P8_DU1], 0>,
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195 InstrStage<1, [P8_DU2], 0>,
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196 InstrStage<1, [P8_LSU1, P8_LSU2,
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197 P8_LU1, P8_LU2], 0>,
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198 InstrStage<1, [P8_FXU1, P8_FXU2,
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199 P8_LU1, P8_LU2]>],
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200 [3, 1, 1]>,
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201 InstrItinData<IIC_LdStLHAU , [InstrStage<1, [P8_DU1], 0>,
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202 InstrStage<1, [P8_DU2], 0>,
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203 InstrStage<1, [P8_LSU1, P8_LSU2,
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204 P8_LU1, P8_LU2], 0>,
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205 InstrStage<1, [P8_FXU1, P8_FXU2]>,
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206 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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207 [4, 4, 1, 1]>,
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208 // first+last in dispatch group.
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209 InstrItinData<IIC_LdStLHAUX , [InstrStage<1, [P8_DU1], 0>,
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210 InstrStage<1, [P8_DU2], 0>,
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211 InstrStage<1, [P8_DU3], 0>,
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212 InstrStage<1, [P8_DU4], 0>,
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213 InstrStage<1, [P8_DU5], 0>,
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214 InstrStage<1, [P8_DU6], 0>,
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215 InstrStage<1, [P8_LSU1, P8_LSU2,
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216 P8_LU1, P8_LU2], 0>,
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217 InstrStage<1, [P8_FXU1, P8_FXU2]>,
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218 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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219 [4, 4, 1, 1]>,
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220 InstrItinData<IIC_LdStLWA , [InstrStage<1, [P8_DU1], 0>,
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221 InstrStage<1, [P8_DU2], 0>,
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222 InstrStage<1, [P8_LSU1, P8_LSU2,
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223 P8_LU1, P8_LU2]>,
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224 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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225 [3, 1, 1]>,
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226 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P8_DU1], 0>,
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227 InstrStage<1, [P8_DU2], 0>,
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228 InstrStage<1, [P8_DU3], 0>,
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229 InstrStage<1, [P8_DU4], 0>,
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230 InstrStage<1, [P8_LSU1, P8_LSU2,
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231 P8_LU1, P8_LU2]>],
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232 [3, 1, 1]>,
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233 // first+last
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234 InstrItinData<IIC_LdStLDARX, [InstrStage<1, [P8_DU1], 0>,
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235 InstrStage<1, [P8_DU2], 0>,
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236 InstrStage<1, [P8_DU3], 0>,
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237 InstrStage<1, [P8_DU4], 0>,
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238 InstrStage<1, [P8_DU5], 0>,
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239 InstrStage<1, [P8_DU6], 0>,
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240 InstrStage<1, [P8_LSU1, P8_LSU2,
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241 P8_LU1, P8_LU2]>],
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242 [3, 1, 1]>,
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243 InstrItinData<IIC_LdStLMW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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244 P8_DU4, P8_DU5, P8_DU6], 0>,
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245 InstrStage<1, [P8_LSU1, P8_LSU2,
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246 P8_LU1, P8_LU2]>],
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247 [2, 1, 1]>,
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248 // Stores are dual-issued from the issue queue, so may only take up one
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249 // dispatch slot. The instruction will be broken into two IOPS. The agen
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250 // op is issued to the LSU, and the data op (register fetch) is issued
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251 // to either the LU (GPR store) or the VSU (FPR store).
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252 InstrItinData<IIC_LdStStore , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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253 P8_DU4, P8_DU5, P8_DU6], 0>,
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254 InstrStage<1, [P8_LSU1, P8_LSU2]>,
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255 InstrStage<1, [P8_LU1, P8_LU2]>],
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256 [1, 1, 1]>,
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257 InstrItinData<IIC_LdStSTD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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258 P8_DU4, P8_DU5, P8_DU6], 0>,
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259 InstrStage<1, [P8_LU1, P8_LU2,
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260 P8_LSU1, P8_LSU2]>]
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261 [1, 1, 1]>,
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262 InstrItinData<IIC_LdStSTDU , [InstrStage<1, [P8_DU1], 0>,
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263 InstrStage<1, [P8_DU2], 0>,
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264 InstrStage<1, [P8_LU1, P8_LU2,
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265 P8_LSU1, P8_LSU2], 0>,
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266 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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267 [2, 1, 1, 1]>,
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268 // First+last
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269 InstrItinData<IIC_LdStSTDUX , [InstrStage<1, [P8_DU1], 0>,
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270 InstrStage<1, [P8_DU2], 0>,
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271 InstrStage<1, [P8_DU3], 0>,
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272 InstrStage<1, [P8_DU4], 0>,
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273 InstrStage<1, [P8_DU5], 0>,
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274 InstrStage<1, [P8_DU6], 0>,
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275 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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276 InstrStage<1, [P8_FXU1, P8_FXU2]>,
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277 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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278 [2, 1, 1, 1]>,
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279 InstrItinData<IIC_LdStSTFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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280 P8_DU4, P8_DU5, P8_DU6], 0>,
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281 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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282 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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283 [1, 1, 1]>,
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284 InstrItinData<IIC_LdStSTFDU , [InstrStage<1, [P8_DU1], 0>,
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285 InstrStage<1, [P8_DU2], 0>,
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286 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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287 InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
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288 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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289 [2, 1, 1, 1]>,
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290 InstrItinData<IIC_LdStSTVEBX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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291 P8_DU4, P8_DU5, P8_DU6], 0>,
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292 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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293 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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294 [1, 1, 1]>,
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295 InstrItinData<IIC_LdStSTDCX , [InstrStage<1, [P8_DU1], 0>,
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296 InstrStage<1, [P8_DU2], 0>,
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297 InstrStage<1, [P8_DU3], 0>,
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298 InstrStage<1, [P8_DU4], 0>,
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299 InstrStage<1, [P8_DU5], 0>,
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300 InstrStage<1, [P8_DU6], 0>,
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301 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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302 InstrStage<1, [P8_LU1, P8_LU2]>],
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303 [1, 1, 1]>,
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304 InstrItinData<IIC_LdStSTWCX , [InstrStage<1, [P8_DU1], 0>,
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305 InstrStage<1, [P8_DU2], 0>,
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306 InstrStage<1, [P8_DU3], 0>,
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307 InstrStage<1, [P8_DU4], 0>,
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308 InstrStage<1, [P8_DU5], 0>,
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309 InstrStage<1, [P8_DU6], 0>,
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310 InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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311 InstrStage<1, [P8_LU1, P8_LU2]>],
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312 [1, 1, 1]>,
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313 InstrItinData<IIC_SprMFCR , [InstrStage<1, [P8_DU1], 0>,
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314 InstrStage<1, [P8_CRU]>],
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315 [6, 1]>,
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316 InstrItinData<IIC_SprMFCRF , [InstrStage<1, [P8_DU1], 0>,
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317 InstrStage<1, [P8_CRU]>],
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318 [3, 1]>,
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319 InstrItinData<IIC_SprMTSPR , [InstrStage<1, [P8_DU1], 0>,
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320 InstrStage<1, [P8_FXU1, P8_FXU2]>],
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321 [4, 1]>, // mtctr
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322 InstrItinData<IIC_FPGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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323 P8_DU4, P8_DU5, P8_DU6], 0>,
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324 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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325 [5, 1, 1]>,
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95
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326 InstrItinData<IIC_FPAddSub , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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327 P8_DU4, P8_DU5, P8_DU6], 0>,
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328 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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329 [5, 1, 1]>,
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83
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330 InstrItinData<IIC_FPCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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331 P8_DU4, P8_DU5, P8_DU6], 0>,
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332 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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333 [8, 1, 1]>,
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334 InstrItinData<IIC_FPDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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335 P8_DU4, P8_DU5, P8_DU6], 0>,
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336 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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337 [33, 1, 1]>,
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338 InstrItinData<IIC_FPDivS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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339 P8_DU4, P8_DU5, P8_DU6], 0>,
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340 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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341 [27, 1, 1]>,
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342 InstrItinData<IIC_FPSqrtD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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343 P8_DU4, P8_DU5, P8_DU6], 0>,
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344 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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345 [44, 1, 1]>,
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346 InstrItinData<IIC_FPSqrtS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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347 P8_DU4, P8_DU5, P8_DU6], 0>,
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348 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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349 [32, 1, 1]>,
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350 InstrItinData<IIC_FPFused , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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351 P8_DU4, P8_DU5, P8_DU6], 0>,
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352 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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353 [5, 1, 1, 1]>,
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354 InstrItinData<IIC_FPRes , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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355 P8_DU4, P8_DU5, P8_DU6], 0>,
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356 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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357 [5, 1, 1]>,
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358 InstrItinData<IIC_VecGeneral , [InstrStage<1, [P8_DU1], 0>,
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359 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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360 [2, 1, 1]>,
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361 InstrItinData<IIC_VecVSL , [InstrStage<1, [P8_DU1], 0>,
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362 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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363 [2, 1, 1]>,
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364 InstrItinData<IIC_VecVSR , [InstrStage<1, [P8_DU1], 0>,
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365 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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366 [2, 1, 1]>,
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367 InstrItinData<IIC_VecFP , [InstrStage<1, [P8_DU1], 0>,
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368 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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369 [6, 1, 1]>,
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370 InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P8_DU1], 0>,
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371 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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372 [6, 1, 1]>,
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373 InstrItinData<IIC_VecFPRound , [InstrStage<1, [P8_DU1], 0>,
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374 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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375 [6, 1, 1]>,
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376 InstrItinData<IIC_VecComplex , [InstrStage<1, [P8_DU1], 0>,
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377 InstrStage<1, [P8_FPU1, P8_FPU2]>],
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378 [7, 1, 1]>,
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379 InstrItinData<IIC_VecPerm , [InstrStage<1, [P8_DU1, P8_DU2], 0>,
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380 InstrStage<1, [P8_FPU2, P8_FPU2]>],
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381 [3, 1, 1]>
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382 ]>;
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383
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384 // ===---------------------------------------------------------------------===//
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385 // P8 machine model for scheduling and other instruction cost heuristics.
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386 // P8 has an 8 insn dispatch group (6 non-branch, 2 branch) and can issue up
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387 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
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388
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389 def P8Model : SchedMachineModel {
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390 let IssueWidth = 8; // up to 8 instructions dispatched per cycle.
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391 // up to six non-branch instructions.
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392 // up to two branches in a dispatch group.
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393
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394 let MinLatency = 0; // Out-of-order dispatch.
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395 let LoadLatency = 3; // Optimistic load latency assuming bypass.
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396 // This is overriden by OperandCycles if the
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397 // Itineraries are queried instead.
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398 let MispredictPenalty = 16;
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399
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400 // Try to make sure we have at least 10 dispatch groups in a loop.
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401 let LoopMicroOpBufferSize = 60;
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402
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403 let Itineraries = P8Itineraries;
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404 }
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405
|
