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annotate lib/Target/PowerPC/PPCTOCRegDeps.cpp @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 //===-- PPCTOCRegDeps.cpp - Add Extra TOC Register Dependencies -----------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // When resolving an address using the ELF ABI TOC pointer, two relocations are
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11 // generally required: one for the high part and one for the low part. Only
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12 // the high part generally explicitly depends on r2 (the TOC pointer). And, so,
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13 // we might produce code like this:
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14 //
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15 // .Ltmp526:
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16 // addis 3, 2, .LC12@toc@ha
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17 // .Ltmp1628:
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18 // std 2, 40(1)
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19 // ld 5, 0(27)
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20 // ld 2, 8(27)
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21 // ld 11, 16(27)
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22 // ld 3, .LC12@toc@l(3)
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23 // rldicl 4, 4, 0, 32
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24 // mtctr 5
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25 // bctrl
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26 // ld 2, 40(1)
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27 //
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28 // And there is nothing wrong with this code, as such, but there is a linker bug
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29 // in binutils (https://sourceware.org/bugzilla/show_bug.cgi?id=18414) that will
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30 // misoptimize this code sequence to this:
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31 // nop
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32 // std r2,40(r1)
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33 // ld r5,0(r27)
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34 // ld r2,8(r27)
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35 // ld r11,16(r27)
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36 // ld r3,-32472(r2)
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37 // clrldi r4,r4,32
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38 // mtctr r5
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39 // bctrl
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40 // ld r2,40(r1)
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41 // because the linker does not know (and does not check) that the value in r2
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42 // changed in between the instruction using the .LC12@toc@ha (TOC-relative)
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43 // relocation and the instruction using the .LC12@toc@l(3) relocation.
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44 // Because it finds these instructions using the relocations (and not by
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45 // scanning the instructions), it has been asserted that there is no good way
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46 // to detect the change of r2 in between. As a result, this bug may never be
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47 // fixed (i.e. it may become part of the definition of the ABI). GCC was
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48 // updated to add extra dependencies on r2 to instructions using the @toc@l
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49 // relocations to avoid this problem, and we'll do the same here.
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50 //
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51 // This is done as a separate pass because:
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52 // 1. These extra r2 dependencies are not really properties of the
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53 // instructions, but rather due to a linker bug, and maybe one day we'll be
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54 // able to get rid of them when targeting linkers without this bug (and,
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55 // thus, keeping the logic centralized here will make that
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56 // straightforward).
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57 // 2. There are ISel-level peephole optimizations that propagate the @toc@l
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58 // relocations to some user instructions, and so the exta dependencies do
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59 // not apply only to a fixed set of instructions (without undesirable
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60 // definition replication).
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61 //
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62 //===----------------------------------------------------------------------===//
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63
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64 #include "PPCInstrInfo.h"
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65 #include "MCTargetDesc/PPCPredicates.h"
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66 #include "PPC.h"
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67 #include "PPCInstrBuilder.h"
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68 #include "PPCMachineFunctionInfo.h"
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69 #include "PPCTargetMachine.h"
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70 #include "llvm/ADT/STLExtras.h"
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71 #include "llvm/ADT/Statistic.h"
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72 #include "llvm/CodeGen/MachineFrameInfo.h"
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73 #include "llvm/CodeGen/MachineFunctionPass.h"
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74 #include "llvm/CodeGen/MachineInstr.h"
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75 #include "llvm/CodeGen/MachineRegisterInfo.h"
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76 #include "llvm/MC/MCAsmInfo.h"
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77 #include "llvm/Support/CommandLine.h"
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78 #include "llvm/Support/Debug.h"
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79 #include "llvm/Support/ErrorHandling.h"
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80 #include "llvm/Support/TargetRegistry.h"
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81 #include "llvm/Support/raw_ostream.h"
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82
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83 using namespace llvm;
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84
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85 #define DEBUG_TYPE "ppc-toc-reg-deps"
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86
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87 namespace llvm {
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88 void initializePPCTOCRegDepsPass(PassRegistry&);
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89 }
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90
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91 namespace {
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92 // PPCTOCRegDeps pass - For simple functions without epilogue code, move
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93 // returns up, and create conditional returns, to avoid unnecessary
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94 // branch-to-blr sequences.
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95 struct PPCTOCRegDeps : public MachineFunctionPass {
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96 static char ID;
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97 PPCTOCRegDeps() : MachineFunctionPass(ID) {
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98 initializePPCTOCRegDepsPass(*PassRegistry::getPassRegistry());
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99 }
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100
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101 protected:
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102 bool hasTOCLoReloc(const MachineInstr &MI) {
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103 if (MI.getOpcode() == PPC::LDtocL ||
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104 MI.getOpcode() == PPC::ADDItocL)
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105 return true;
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106
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107 for (const MachineOperand &MO : MI.operands()) {
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108 if ((MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) == PPCII::MO_TOC_LO)
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109 return true;
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110 }
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111
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112 return false;
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113 }
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114
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115 bool processBlock(MachineBasicBlock &MBB) {
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116 bool Changed = false;
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117
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118 for (auto &MI : MBB) {
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119 if (!hasTOCLoReloc(MI))
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120 continue;
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121
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122 MI.addOperand(MachineOperand::CreateReg(PPC::X2,
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123 false /*IsDef*/,
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124 true /*IsImp*/));
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125 Changed = true;
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126 }
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127
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128 return Changed;
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129 }
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130
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131 public:
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132 bool runOnMachineFunction(MachineFunction &MF) override {
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133 bool Changed = false;
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134
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135 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
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136 MachineBasicBlock &B = *I++;
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137 if (processBlock(B))
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138 Changed = true;
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139 }
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140
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141 return Changed;
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142 }
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143
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144 void getAnalysisUsage(AnalysisUsage &AU) const override {
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145 MachineFunctionPass::getAnalysisUsage(AU);
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146 }
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147 };
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148 }
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149
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150 INITIALIZE_PASS(PPCTOCRegDeps, DEBUG_TYPE,
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151 "PowerPC TOC Register Dependencies", false, false)
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152
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153 char PPCTOCRegDeps::ID = 0;
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154 FunctionPass*
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155 llvm::createPPCTOCRegDepsPass() { return new PPCTOCRegDeps(); }
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156