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annotate test/CodeGen/ARM/2010-05-21-BuildVector.ll @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children
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1 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
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2 ; Radar 7872877
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3
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4 define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind {
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5 entry:
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6 %0 = load float, float* %fltp
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7 %1 = insertelement <4 x float> undef, float %0, i32 0
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8 %2 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer
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9 %3 = shl i32 %packedValue, 16
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10 %4 = ashr i32 %3, 30
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11 %.sum = add i32 %4, 4
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12 %5 = getelementptr inbounds float, float* %table, i32 %.sum
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13 ;CHECK: vldr s
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14 %6 = load float, float* %5, align 4
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15 %tmp11 = insertelement <4 x float> undef, float %6, i32 0
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16 %7 = shl i32 %packedValue, 18
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17 %8 = ashr i32 %7, 30
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18 %.sum12 = add i32 %8, 4
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19 %9 = getelementptr inbounds float, float* %table, i32 %.sum12
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20 ;CHECK: vldr s
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21 %10 = load float, float* %9, align 4
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22 %tmp9 = insertelement <4 x float> %tmp11, float %10, i32 1
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23 %11 = shl i32 %packedValue, 20
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24 %12 = ashr i32 %11, 30
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25 %.sum13 = add i32 %12, 4
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26 %13 = getelementptr inbounds float, float* %table, i32 %.sum13
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27 ;CHECK: vldr s
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28 %14 = load float, float* %13, align 4
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29 %tmp7 = insertelement <4 x float> %tmp9, float %14, i32 2
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30 %15 = shl i32 %packedValue, 22
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31 %16 = ashr i32 %15, 30
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32 %.sum14 = add i32 %16, 4
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33 %17 = getelementptr inbounds float, float* %table, i32 %.sum14
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34 ;CHECK: vldr s
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35 %18 = load float, float* %17, align 4
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36 %tmp5 = insertelement <4 x float> %tmp7, float %18, i32 3
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37 %19 = fmul <4 x float> %tmp5, %2
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38 %20 = bitcast float* %fltp to i8*
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39 tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %20, <4 x float> %19, i32 1)
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40 ret void
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41 }
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43 declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind