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annotate test/CodeGen/ARM/gep-optimization.ll @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children
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afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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1 ; RUN: llc < %s -mtriple=armv7a-eabi | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-AT2
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2 ; RUN: llc < %s -mtriple=thumbv7m-eabi | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-AT2
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3 ; RUN: llc < %s -mtriple=thumbv6m-eabi | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T1
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4
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5 ; This test checks that various kinds of getelementptr are all optimised to a
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6 ; simple multiply plus add, with the add being done by a register offset if the
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7 ; result is used in a load.
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8
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9 ; CHECK-LABEL: calc_1d:
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10 ; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84
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11 ; CHECK-AT2: mla r0, r1, [[REG1]], r0
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12 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
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13 ; CHECK-T1: adds r0, r0, [[REG2]]
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14 define i32* @calc_1d(i32* %p, i32 %n) {
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15 entry:
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16 %mul = mul nsw i32 %n, 21
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17 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %mul
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18 ret i32* %add.ptr
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19 }
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20
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21 ; CHECK-LABEL: load_1d:
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22 ; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84
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23 ; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
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24 ; CHECK: ldr r0, [r0, [[REG2]]]
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25 define i32 @load_1d(i32* %p, i32 %n) #1 {
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26 entry:
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27 %mul = mul nsw i32 %n, 21
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28 %arrayidx = getelementptr inbounds i32, i32* %p, i32 %mul
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29 %0 = load i32, i32* %arrayidx, align 4
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30 ret i32 %0
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31 }
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32
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33 ; CHECK-LABEL: calc_2d_a:
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34 ; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84
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35 ; CHECK-AT2: mla r0, r1, [[REG1]], r0
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36 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
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37 ; CHECK-T1: adds r0, r0, [[REG2]]
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38 define i32* @calc_2d_a([100 x i32]* %p, i32 %n) {
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39 entry:
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40 %mul = mul nsw i32 %n, 21
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41 %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %p, i32 0, i32 %mul
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42 ret i32* %arrayidx1
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43 }
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44
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45 ; CHECK-LABEL: load_2d_a:
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46 ; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84
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47 ; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
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48 ; CHECK: ldr r0, [r0, [[REG2]]]
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49 define i32 @load_2d_a([100 x i32]* %p, i32 %n) #1 {
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50 entry:
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51 %mul = mul nsw i32 %n, 21
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52 %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %p, i32 0, i32 %mul
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53 %0 = load i32, i32* %arrayidx1, align 4
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54 ret i32 %0
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55 }
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56
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57 ; CHECK-LABEL: calc_2d_b:
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58 ; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84
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59 ; CHECK-AT2: mla r0, r1, [[REG1]], r0
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60 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
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61 ; CHECK-T1: adds r0, r0, [[REG2]]
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62 define i32* @calc_2d_b([21 x i32]* %p, i32 %n) {
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63 entry:
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64 %arrayidx1 = getelementptr inbounds [21 x i32], [21 x i32]* %p, i32 %n, i32 0
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65 ret i32* %arrayidx1
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66 }
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67
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68 ; CHECK-LABEL: load_2d_b:
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69 ; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84
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70 ; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
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71 ; CHECK: ldr r0, [r0, [[REG2]]]
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72 define i32 @load_2d_b([21 x i32]* %p, i32 %n) {
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73 entry:
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74 %arrayidx1 = getelementptr inbounds [21 x i32], [21 x i32]* %p, i32 %n, i32 0
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75 %0 = load i32, i32* %arrayidx1, align 4
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76 ret i32 %0
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77 }