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annotate test/CodeGen/ARM/machine-licm.ll @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children
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95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=THUMB
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2 ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=ARM
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3 ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim -mattr=+v6t2 | FileCheck %s -check-prefix=MOVT
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4 ; rdar://7353541
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5 ; rdar://7354376
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6 ; rdar://8887598
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8 @GV = external global i32 ; <i32*> [#uses=2]
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10 define void @t(i32* nocapture %vals, i32 %c) nounwind {
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11 entry:
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12 ; ARM-LABEL: t:
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13 ; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
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14 ; ARM: LPC0_0:
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15 ; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
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16 ; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
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18 ; MOVT-LABEL: t:
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19 ; MOVT: movw [[REGISTER_2:r[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+8))
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20 ; MOVT: movt [[REGISTER_2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+8))
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21 ; MOVT: LPC0_0:
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22 ; MOVT: ldr r{{[0-9]+}}, [pc, [[REGISTER_2]]]
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23 ; MOVT: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
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24
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25 ; THUMB-LABEL: t:
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26 %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
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27 br i1 %0, label %return, label %bb.nph
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28
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29 bb.nph: ; preds = %entry
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30 ; ARM: LCPI0_0:
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e4204d083e25 LLVM 3.5
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31 ; ARM-NOT: LCPI0_1:
0
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32 ; ARM: .section
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33
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34 ; THUMB: BB#1
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35 ; THUMB: ldr r2, LCPI0_0
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36 ; THUMB: add r2, pc
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37 ; THUMB: ldr r{{[0-9]+}}, [r2]
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38 ; THUMB: LBB0_2
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39 ; THUMB: LCPI0_0:
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40 ; THUMB-NOT: LCPI0_1:
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41 ; THUMB: .section
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afa8332a0e37 LLVM 3.8
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42 %.pre = load i32, i32* @GV, align 4 ; <i32> [#uses=1]
0
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43 br label %bb
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44
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45 bb: ; preds = %bb, %bb.nph
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46 %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1]
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47 %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2]
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48 %scevgep = getelementptr i32, i32* %vals, i32 %i.03 ; <i32*> [#uses=1]
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49 %2 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1]
0
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50 %3 = add nsw i32 %1, %2 ; <i32> [#uses=2]
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51 store i32 %3, i32* @GV, align 4
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52 %4 = add i32 %i.03, 1 ; <i32> [#uses=2]
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53 %exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1]
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54 br i1 %exitcond, label %return, label %bb
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55
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56 return: ; preds = %bb, %entry
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57 ret void
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58 }