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annotate test/CodeGen/ARM/neon_ld2.ll @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children
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54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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1 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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2 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mcpu=swift %s -o - | FileCheck %s --check-prefix=SWIFT
0
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3
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4 ; CHECK: t1
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5 ; CHECK: vld1.64
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6 ; CHECK: vld1.64
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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7 ; CHECK: vadd.i64 q
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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8 ; CHECK: vst1.64
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9 ; SWIFT: t1
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10 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
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11 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
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12 ; SWIFT: vadd.i64 q
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13 ; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
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14 define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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15 entry:
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afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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16 %0 = load <2 x i64>, <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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17 %1 = load <2 x i64>, <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1]
0
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18 %2 = add <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]
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19 %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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20 store <4 x i32> %3, <4 x i32>* %r, align 16
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21 ret void
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22 }
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23
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24 ; CHECK: t2
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25 ; CHECK: vld1.64
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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26 ; CHECK: vld1.64
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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27 ; CHECK: vsub.i64 q
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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28 ; CHECK: vmov r0, r1, d
95c75e76d11b LLVM 3.4
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29 ; CHECK: vmov r2, r3, d
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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30 ; SWIFT: t2
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31 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
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32 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
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33 ; SWIFT: vsub.i64 q
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34 ; SWIFT: vmov r0, r1, d
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35 ; SWIFT: vmov r2, r3, d
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36 define <4 x i32> @t2(<2 x i64>* %a, <2 x i64>* %b) nounwind readonly {
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37 entry:
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afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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38 %0 = load <2 x i64>, <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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39 %1 = load <2 x i64>, <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1]
0
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40 %2 = sub <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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41 %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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42 ret <4 x i32> %3
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43 }
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44
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45 ; Limited alignment.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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46 ; SWIFT: t3
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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47 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}
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48 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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49 ; SWIFT: vadd.i64 q
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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50 ; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}
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51 define void @t3(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
95c75e76d11b LLVM 3.4
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52 entry:
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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53 %0 = load <2 x i64>, <2 x i64>* %a, align 8
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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54 %1 = load <2 x i64>, <2 x i64>* %b, align 8
0
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parents:
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55 %2 = add <2 x i64> %0, %1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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56 %3 = bitcast <2 x i64> %2 to <4 x i32>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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57 store <4 x i32> %3, <4 x i32>* %r, align 8
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58 ret void
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parents:
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59 }