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annotate test/CodeGen/ARM/swift-vldm.ll @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s
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3 ; Check that we avoid producing vldm instructions using d registers that
95c75e76d11b LLVM 3.4
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4 ; begin in the most-significant half of a q register. These require more
95c75e76d11b LLVM 3.4
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5 ; micro-ops on swift and so aren't worth combining.
95c75e76d11b LLVM 3.4
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7 ; CHECK-LABEL: test_vldm
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8 ; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4}
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9 ; CHECK-NOT: vldmia r{{[0-9]+}}, {d1, d2, d3, d4}
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95c75e76d11b LLVM 3.4
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11 declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
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95c75e76d11b LLVM 3.4
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13 define void @test_vldm(double* %x, double * %y) {
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14 entry:
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afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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15 %addr1 = getelementptr double, double * %x, i32 1
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16 %addr2 = getelementptr double, double * %x, i32 2
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17 %addr3 = getelementptr double, double * %x, i32 3
afa8332a0e37 LLVM 3.8
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18 %d0 = load double , double * %y
afa8332a0e37 LLVM 3.8
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19 %d1 = load double , double * %x
afa8332a0e37 LLVM 3.8
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20 %d2 = load double , double * %addr1
afa8332a0e37 LLVM 3.8
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21 %d3 = load double , double * %addr2
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22 %d4 = load double , double * %addr3
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23 ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we
95c75e76d11b LLVM 3.4
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24 ; don't form a "vldmia rX, {d1, d2, d3, d4}".
95c75e76d11b LLVM 3.4
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25 ; We are relying on the calling convention and that register allocation
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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26 ; properly coalesces registers.
95c75e76d11b LLVM 3.4
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27 call fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
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28 ret void
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29 }