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annotate test/CodeGen/ARM/vneg.ll @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
0
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2
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3 define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
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4 ;CHECK-LABEL: vnegs8:
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5 ;CHECK: vneg.s8
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parents: 77
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6 %tmp1 = load <8 x i8>, <8 x i8>* %A
0
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7 %tmp2 = sub <8 x i8> zeroinitializer, %tmp1
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8 ret <8 x i8> %tmp2
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9 }
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10
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11 define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
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12 ;CHECK-LABEL: vnegs16:
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parents:
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13 ;CHECK: vneg.s16
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parents: 77
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14 %tmp1 = load <4 x i16>, <4 x i16>* %A
0
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15 %tmp2 = sub <4 x i16> zeroinitializer, %tmp1
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16 ret <4 x i16> %tmp2
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17 }
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18
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19 define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
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20 ;CHECK-LABEL: vnegs32:
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21 ;CHECK: vneg.s32
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22 %tmp1 = load <2 x i32>, <2 x i32>* %A
0
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23 %tmp2 = sub <2 x i32> zeroinitializer, %tmp1
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24 ret <2 x i32> %tmp2
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25 }
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26
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27 define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
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28 ;CHECK-LABEL: vnegf32:
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29 ;CHECK: vneg.f32
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30 %tmp1 = load <2 x float>, <2 x float>* %A
0
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31 %tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
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32 ret <2 x float> %tmp2
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33 }
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34
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35 define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
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36 ;CHECK-LABEL: vnegQs8:
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37 ;CHECK: vneg.s8
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38 %tmp1 = load <16 x i8>, <16 x i8>* %A
0
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39 %tmp2 = sub <16 x i8> zeroinitializer, %tmp1
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40 ret <16 x i8> %tmp2
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41 }
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42
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43 define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
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44 ;CHECK-LABEL: vnegQs16:
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45 ;CHECK: vneg.s16
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parents: 77
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46 %tmp1 = load <8 x i16>, <8 x i16>* %A
0
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47 %tmp2 = sub <8 x i16> zeroinitializer, %tmp1
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48 ret <8 x i16> %tmp2
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49 }
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50
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51 define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
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52 ;CHECK-LABEL: vnegQs32:
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53 ;CHECK: vneg.s32
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parents: 77
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54 %tmp1 = load <4 x i32>, <4 x i32>* %A
0
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parents:
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55 %tmp2 = sub <4 x i32> zeroinitializer, %tmp1
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56 ret <4 x i32> %tmp2
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57 }
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58
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59 define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
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60 ;CHECK-LABEL: vnegQf32:
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61 ;CHECK: vneg.f32
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62 %tmp1 = load <4 x float>, <4 x float>* %A
0
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63 %tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
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64 ret <4 x float> %tmp2
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65 }
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66
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67 define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
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68 ;CHECK-LABEL: vqnegs8:
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69 ;CHECK: vqneg.s8
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70 %tmp1 = load <8 x i8>, <8 x i8>* %A
0
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71 %tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
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72 ret <8 x i8> %tmp2
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73 }
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74
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75 define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
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76 ;CHECK-LABEL: vqnegs16:
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77 ;CHECK: vqneg.s16
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78 %tmp1 = load <4 x i16>, <4 x i16>* %A
0
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79 %tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
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80 ret <4 x i16> %tmp2
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81 }
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82
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83 define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
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84 ;CHECK-LABEL: vqnegs32:
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85 ;CHECK: vqneg.s32
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86 %tmp1 = load <2 x i32>, <2 x i32>* %A
0
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87 %tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
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88 ret <2 x i32> %tmp2
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89 }
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90
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91 define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
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92 ;CHECK-LABEL: vqnegQs8:
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93 ;CHECK: vqneg.s8
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94 %tmp1 = load <16 x i8>, <16 x i8>* %A
0
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95 %tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
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96 ret <16 x i8> %tmp2
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97 }
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98
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99 define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
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100 ;CHECK-LABEL: vqnegQs16:
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101 ;CHECK: vqneg.s16
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102 %tmp1 = load <8 x i16>, <8 x i16>* %A
0
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103 %tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
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104 ret <8 x i16> %tmp2
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105 }
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106
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107 define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
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108 ;CHECK-LABEL: vqnegQs32:
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109 ;CHECK: vqneg.s32
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110 %tmp1 = load <4 x i32>, <4 x i32>* %A
0
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111 %tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
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112 ret <4 x i32> %tmp2
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113 }
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114
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115 declare <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8>) nounwind readnone
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parents:
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116 declare <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16>) nounwind readnone
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parents:
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117 declare <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32>) nounwind readnone
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118
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parents:
diff changeset
119 declare <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8>) nounwind readnone
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
120 declare <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16>) nounwind readnone
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
121 declare <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32>) nounwind readnone