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annotate test/CodeGen/ARM/vrev.ll @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
0
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2
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3 define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
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4 ;CHECK-LABEL: test_vrev64D8:
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5 ;CHECK: vrev64.8
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6 %tmp1 = load <8 x i8>, <8 x i8>* %A
0
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7 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
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8 ret <8 x i8> %tmp2
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9 }
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10
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11 define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
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12 ;CHECK-LABEL: test_vrev64D16:
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13 ;CHECK: vrev64.16
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14 %tmp1 = load <4 x i16>, <4 x i16>* %A
0
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15 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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16 ret <4 x i16> %tmp2
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17 }
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18
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19 define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
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20 ;CHECK-LABEL: test_vrev64D32:
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21 ;CHECK: vrev64.32
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22 %tmp1 = load <2 x i32>, <2 x i32>* %A
0
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23 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
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24 ret <2 x i32> %tmp2
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25 }
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26
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27 define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
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28 ;CHECK-LABEL: test_vrev64Df:
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29 ;CHECK: vrev64.32
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30 %tmp1 = load <2 x float>, <2 x float>* %A
0
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31 %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
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32 ret <2 x float> %tmp2
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33 }
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34
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35 define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
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36 ;CHECK-LABEL: test_vrev64Q8:
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37 ;CHECK: vrev64.8
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38 %tmp1 = load <16 x i8>, <16 x i8>* %A
0
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39 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
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40 ret <16 x i8> %tmp2
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41 }
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42
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43 define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
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44 ;CHECK-LABEL: test_vrev64Q16:
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45 ;CHECK: vrev64.16
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46 %tmp1 = load <8 x i16>, <8 x i16>* %A
0
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47 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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48 ret <8 x i16> %tmp2
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49 }
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50
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51 define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
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52 ;CHECK-LABEL: test_vrev64Q32:
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53 ;CHECK: vrev64.32
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54 %tmp1 = load <4 x i32>, <4 x i32>* %A
0
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55 %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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56 ret <4 x i32> %tmp2
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57 }
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58
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59 define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
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60 ;CHECK-LABEL: test_vrev64Qf:
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61 ;CHECK: vrev64.32
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62 %tmp1 = load <4 x float>, <4 x float>* %A
0
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63 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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64 ret <4 x float> %tmp2
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65 }
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66
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67 define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
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68 ;CHECK-LABEL: test_vrev32D8:
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69 ;CHECK: vrev32.8
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70 %tmp1 = load <8 x i8>, <8 x i8>* %A
0
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71 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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72 ret <8 x i8> %tmp2
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73 }
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74
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75 define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
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76 ;CHECK-LABEL: test_vrev32D16:
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77 ;CHECK: vrev32.16
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78 %tmp1 = load <4 x i16>, <4 x i16>* %A
0
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79 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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80 ret <4 x i16> %tmp2
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81 }
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82
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83 define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
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84 ;CHECK-LABEL: test_vrev32Q8:
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85 ;CHECK: vrev32.8
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86 %tmp1 = load <16 x i8>, <16 x i8>* %A
0
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87 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
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88 ret <16 x i8> %tmp2
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89 }
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90
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91 define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
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92 ;CHECK-LABEL: test_vrev32Q16:
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93 ;CHECK: vrev32.16
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94 %tmp1 = load <8 x i16>, <8 x i16>* %A
0
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95 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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96 ret <8 x i16> %tmp2
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97 }
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98
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99 define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
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100 ;CHECK-LABEL: test_vrev16D8:
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101 ;CHECK: vrev16.8
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102 %tmp1 = load <8 x i8>, <8 x i8>* %A
0
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103 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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104 ret <8 x i8> %tmp2
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105 }
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106
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107 define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
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108 ;CHECK-LABEL: test_vrev16Q8:
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109 ;CHECK: vrev16.8
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110 %tmp1 = load <16 x i8>, <16 x i8>* %A
0
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111 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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parents:
diff changeset
112 ret <16 x i8> %tmp2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
113 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
114
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
115 ; Undef shuffle indices should not prevent matching to VREV:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
116
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
117 define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
118 ;CHECK-LABEL: test_vrev64D8_undef:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
119 ;CHECK: vrev64.8
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
120 %tmp1 = load <8 x i8>, <8 x i8>* %A
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
121 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
122 ret <8 x i8> %tmp2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
123 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
124
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
125 define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
126 ;CHECK-LABEL: test_vrev32Q16_undef:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
127 ;CHECK: vrev32.16
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
128 %tmp1 = load <8 x i16>, <8 x i16>* %A
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
129 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
130 ret <8 x i16> %tmp2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
131 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
132
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
133 ; A vcombine feeding a VREV should not obscure things. Radar 8597007.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
134
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
135 define void @test_with_vcombine(<4 x float>* %v) nounwind {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
136 ;CHECK-LABEL: test_with_vcombine:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
137 ;CHECK-NOT: vext
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
138 ;CHECK: vrev64.32
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
139 %tmp1 = load <4 x float>, <4 x float>* %v, align 16
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
140 %tmp2 = bitcast <4 x float> %tmp1 to <2 x double>
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
141 %tmp3 = extractelement <2 x double> %tmp2, i32 0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 %tmp4 = bitcast double %tmp3 to <2 x float>
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
143 %tmp5 = extractelement <2 x double> %tmp2, i32 1
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 %tmp6 = bitcast double %tmp5 to <2 x float>
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 %tmp7 = fadd <2 x float> %tmp6, %tmp6
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 %tmp8 = shufflevector <2 x float> %tmp4, <2 x float> %tmp7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
147 store <4 x float> %tmp8, <4 x float>* %v, align 16
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
148 ret void
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
149 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
150
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 ; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 ; to <2 x i16> when stored to memory.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
153 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 ; CHECK-LABEL: test_vrev64:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
155 ; CHECK: vst1.32
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 entry:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
157 %0 = bitcast <4 x i16>* %source to <8 x i16>*
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
158 %tmp2 = load <8 x i16>, <8 x i16>* %0, align 4
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
159 %tmp3 = extractelement <8 x i16> %tmp2, i32 6
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
160 %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
161 %tmp9 = extractelement <8 x i16> %tmp2, i32 5
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
162 %tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
163 store <2 x i16> %tmp11, <2 x i16>* %dst, align 4
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
164 ret void
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
166
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 ; Test vrev of float4
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
168 define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
169 ; CHECK: float_vrev64
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 ; CHECK: vext.32
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
171 ; CHECK: vrev64.32
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
172 entry:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
173 %0 = bitcast float* %source to <4 x float>*
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
174 %tmp2 = load <4 x float>, <4 x float>* %0, align 4
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
176 %arrayidx8 = getelementptr inbounds <4 x float>, <4 x float>* %dest, i32 11
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
177 store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
178 ret void
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
179 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
180
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
181 define <4 x i32> @test_vrev32_bswap(<4 x i32> %source) nounwind {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
182 ; CHECK-LABEL: test_vrev32_bswap:
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
183 ; CHECK: vrev32.8
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
184 %bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %source)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
185 ret <4 x i32> %bswap
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
186 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
187
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
188 declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone