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annotate test/CodeGen/NVPTX/fma.ll @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents 60c9769439b8
children 803732b1fca8
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54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -fp-contract=fast | FileCheck %s
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2
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
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3 declare float @dummy_f32(float, float) #0
60c9769439b8 LLVM 3.7
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4 declare double @dummy_f64(double, double) #0
60c9769439b8 LLVM 3.7
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5
0
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6 define ptx_device float @t1_f32(float %x, float %y, float %z) {
95c75e76d11b LLVM 3.4
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7 ; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
95c75e76d11b LLVM 3.4
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8 ; CHECK: ret;
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9 %a = fmul float %x, %y
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10 %b = fadd float %a, %z
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11 ret float %b
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12 }
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13
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60c9769439b8 LLVM 3.7
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14 define ptx_device float @t2_f32(float %x, float %y, float %z, float %w) {
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15 ; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
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16 ; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
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17 ; CHECK: ret;
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18 %a = fmul float %x, %y
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19 %b = fadd float %a, %z
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20 %c = fadd float %a, %w
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21 %d = call float @dummy_f32(float %b, float %c)
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22 ret float %d
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23 }
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24
0
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25 define ptx_device double @t1_f64(double %x, double %y, double %z) {
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54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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26 ; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
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27 ; CHECK: ret;
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28 %a = fmul double %x, %y
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29 %b = fadd double %a, %z
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30 ret double %b
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31 }
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32
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33 define ptx_device double @t2_f64(double %x, double %y, double %z, double %w) {
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34 ; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
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35 ; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
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36 ; CHECK: ret;
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37 %a = fmul double %x, %y
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38 %b = fadd double %a, %z
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39 %c = fadd double %a, %w
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40 %d = call double @dummy_f64(double %b, double %c)
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41 ret double %d
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42 }