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annotate docs/AMDGPUUsage.rst @ 107:a03ddd01be7e

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author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Sun, 31 Jan 2016 17:34:49 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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1 ==============================
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2 User Guide for AMDGPU Back-end
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3 ==============================
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4
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5 Introduction
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6 ============
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7
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8 The AMDGPU back-end provides ISA code generation for AMD GPUs, starting with
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9 the R600 family up until the current Volcanic Islands (GCN Gen 3).
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10
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11
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12 Assembler
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13 =========
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14
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15 The assembler is currently considered experimental.
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16
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17 For syntax examples look in test/MC/AMDGPU.
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18
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19 Below some of the currently supported features (modulo bugs). These
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20 all apply to the Southern Islands ISA, Sea Islands and Volcanic Islands
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21 are also supported but may be missing some instructions and have more bugs:
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22
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23 DS Instructions
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24 ---------------
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25 All DS instructions are supported.
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26
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27 FLAT Instructions
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28 ------------------
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29 These instructions are only present in the Sea Islands and Volcanic Islands
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30 instruction set. All FLAT instructions are supported for these architectures
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31
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32 MUBUF Instructions
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33 ------------------
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34 All non-atomic MUBUF instructions are supported.
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35
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36 SMRD Instructions
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37 -----------------
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38 Only the s_load_dword* SMRD instructions are supported.
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39
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40 SOP1 Instructions
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41 -----------------
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42 All SOP1 instructions are supported.
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43
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44 SOP2 Instructions
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45 -----------------
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46 All SOP2 instructions are supported.
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47
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48 SOPC Instructions
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49 -----------------
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50 All SOPC instructions are supported.
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51
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52 SOPP Instructions
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53 -----------------
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54
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55 Unless otherwise mentioned, all SOPP instructions that have one or more
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56 operands accept integer operands only. No verification is performed
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57 on the operands, so it is up to the programmer to be familiar with the
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58 range or acceptable values.
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59
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60 s_waitcnt
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61 ^^^^^^^^^
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62
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63 s_waitcnt accepts named arguments to specify which memory counter(s) to
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64 wait for.
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65
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66 .. code-block:: nasm
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67
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68 // Wait for all counters to be 0
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69 s_waitcnt 0
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70
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71 // Equivalent to s_waitcnt 0. Counter names can also be delimited by
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72 // '&' or ','.
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73 s_waitcnt vmcnt(0) expcnt(0) lgkcmt(0)
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74
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75 // Wait for vmcnt counter to be 1.
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76 s_waitcnt vmcnt(1)
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77
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78 VOP1, VOP2, VOP3, VOPC Instructions
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79 -----------------------------------
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80
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81 All 32-bit and 64-bit encodings should work.
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82
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83 The assembler will automatically detect which encoding size to use for
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84 VOP1, VOP2, and VOPC instructions based on the operands. If you want to force
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85 a specific encoding size, you can add an _e32 (for 32-bit encoding) or
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86 _e64 (for 64-bit encoding) suffix to the instruction. Most, but not all
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87 instructions support an explicit suffix. These are all valid assembly
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88 strings:
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89
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90 .. code-block:: nasm
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91
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92 v_mul_i32_i24 v1, v2, v3
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93 v_mul_i32_i24_e32 v1, v2, v3
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94 v_mul_i32_i24_e64 v1, v2, v3
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95
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96 Assembler Directives
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97 --------------------
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98
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99 .hsa_code_object_version major, minor
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100 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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101
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102 *major* and *minor* are integers that specify the version of the HSA code
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103 object that will be generated by the assembler. This value will be stored
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104 in an entry of the .note section.
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105
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106 .hsa_code_object_isa [major, minor, stepping, vendor, arch]
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107 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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108
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109 *major*, *minor*, and *stepping* are all integers that describe the instruction
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110 set architecture (ISA) version of the assembly program.
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111
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112 *vendor* and *arch* are quoted strings. *vendor* should always be equal to
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113 "AMD" and *arch* should always be equal to "AMDGPU".
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114
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115 If no arguments are specified, then the assembler will derive the ISA version,
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116 *vendor*, and *arch* from the value of the -mcpu option that is passed to the
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117 assembler.
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118
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119 ISA version, *vendor*, and *arch* will all be stored in a single entry of the
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120 .note section.
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121
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122 .amd_kernel_code_t
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123 ^^^^^^^^^^^^^^^^^^
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124
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125 This directive marks the beginning of a list of key / value pairs that are used
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126 to specify the amd_kernel_code_t object that will be emitted by the assembler.
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127 The list must be terminated by the *.end_amd_kernel_code_t* directive. For
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128 any amd_kernel_code_t values that are unspecified a default value will be
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129 used. The default value for all keys is 0, with the following exceptions:
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130
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131 - *kernel_code_version_major* defaults to 1.
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132 - *machine_kind* defaults to 1.
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133 - *machine_version_major*, *machine_version_minor*, and
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134 *machine_version_stepping* are derived from the value of the -mcpu option
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135 that is passed to the assembler.
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136 - *kernel_code_entry_byte_offset* defaults to 256.
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137 - *wavefront_size* defaults to 6.
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138 - *kernarg_segment_alignment*, *group_segment_alignment*, and
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139 *private_segment_alignment* default to 4. Note that alignments are specified
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140 as a power of two, so a value of **n** means an alignment of 2^ **n**.
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141
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142 The *.amd_kernel_code_t* directive must be placed immediately after the
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143 function label and before any instructions.
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144
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145 For a full list of amd_kernel_code_t keys, see the examples in
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146 test/CodeGen/AMDGPU/hsa.s. For an explanation of the meanings of the different
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147 keys, see the comments in lib/Target/AMDGPU/AmdKernelCodeT.h
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148
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149 Here is an example of a minimal amd_kernel_code_t specification:
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150
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151 .. code-block:: nasm
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152
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153 .hsa_code_object_version 1,0
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154 .hsa_code_object_isa
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155
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156 .text
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157
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158 hello_world:
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159
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160 .amd_kernel_code_t
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161 enable_sgpr_kernarg_segment_ptr = 1
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162 is_ptr64 = 1
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163 compute_pgm_rsrc1_vgprs = 0
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164 compute_pgm_rsrc1_sgprs = 0
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165 compute_pgm_rsrc2_user_sgpr = 2
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166 kernarg_segment_byte_size = 8
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167 wavefront_sgpr_count = 2
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168 workitem_vgpr_count = 3
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169 .end_amd_kernel_code_t
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170
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171 s_load_dwordx2 s[0:1], s[0:1] 0x0
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172 v_mov_b32 v0, 3.14159
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173 s_waitcnt lgkmcnt(0)
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174 v_mov_b32 v1, s0
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175 v_mov_b32 v2, s1
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176 flat_store_dword v0, v[1:2]
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177 s_endpgm