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annotate lib/Target/ARM/ARMSelectionDAGInfo.h @ 20:a5b470e0d09d

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set FastCC(Calling Convention) when the function is code segment and set GuaranteedTailCallOpt. but llvm still output not jmp but call...
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Sun, 06 Oct 2013 18:16:15 +0900
parents 9ad51c7bc036
children
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1 //===-- ARMSelectionDAGInfo.h - ARM SelectionDAG Info -----------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the ARM subclass for TargetSelectionDAGInfo.
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11 //
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12 //===----------------------------------------------------------------------===//
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14 #ifndef ARMSELECTIONDAGINFO_H
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15 #define ARMSELECTIONDAGINFO_H
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17 #include "MCTargetDesc/ARMAddressingModes.h"
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18 #include "llvm/Target/TargetSelectionDAGInfo.h"
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20 namespace llvm {
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21
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22 namespace ARM_AM {
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23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
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24 switch (Opcode) {
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25 default: return ARM_AM::no_shift;
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26 case ISD::SHL: return ARM_AM::lsl;
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27 case ISD::SRL: return ARM_AM::lsr;
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28 case ISD::SRA: return ARM_AM::asr;
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29 case ISD::ROTR: return ARM_AM::ror;
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30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
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31 // Can't handle RRX here, because it would require folding a flag into
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32 // the addressing mode. :( This causes us to miss certain things.
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33 //case ARMISD::RRX: return ARM_AM::rrx;
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34 }
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35 }
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36 } // end namespace ARM_AM
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38 class ARMSelectionDAGInfo : public TargetSelectionDAGInfo {
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39 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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40 /// make the right decision when generating code for different targets.
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41 const ARMSubtarget *Subtarget;
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43 public:
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44 explicit ARMSelectionDAGInfo(const TargetMachine &TM);
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45 ~ARMSelectionDAGInfo();
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47 virtual
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48 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
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49 SDValue Chain,
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50 SDValue Dst, SDValue Src,
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51 SDValue Size, unsigned Align,
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52 bool isVolatile, bool AlwaysInline,
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53 MachinePointerInfo DstPtrInfo,
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54 MachinePointerInfo SrcPtrInfo) const;
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55
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56 // Adjust parameters for memset, see RTABI section 4.3.4
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57 virtual
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58 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
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59 SDValue Chain,
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60 SDValue Op1, SDValue Op2,
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61 SDValue Op3, unsigned Align,
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62 bool isVolatile,
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63 MachinePointerInfo DstPtrInfo) const;
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64 };
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65
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66 }
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67
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68 #endif