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annotate lib/Target/X86/X86InstrCMovSetCC.td @ 116:a609e5c42ecc

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change from CGF to this
author mir3636
date Mon, 08 Aug 2016 19:47:00 +0900
parents afa8332a0e37
children 803732b1fca8
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1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file describes the X86 conditional move and set on condition
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11 // instructions.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15
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16 // CMOV instructions.
0
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17 multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
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18 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
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19 isCommutable = 1, SchedRW = [WriteALU] in {
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20 def NAME#16rr
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21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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22 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
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23 [(set GR16:$dst,
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24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
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25 IIC_CMOV16_RR>, TB, OpSize16;
0
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26 def NAME#32rr
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27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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28 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
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29 [(set GR32:$dst,
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30 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
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31 IIC_CMOV32_RR>, TB, OpSize32;
0
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32 def NAME#64rr
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33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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34 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
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35 [(set GR64:$dst,
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36 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))],
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37 IIC_CMOV32_RR>, TB;
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38 }
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39
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40 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
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41 SchedRW = [WriteALULd, ReadAfterLd] in {
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42 def NAME#16rm
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43 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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44 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
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45 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
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46 CondNode, EFLAGS))], IIC_CMOV16_RM>,
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47 TB, OpSize16;
0
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48 def NAME#32rm
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49 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
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50 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
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51 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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52 CondNode, EFLAGS))], IIC_CMOV32_RM>,
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53 TB, OpSize32;
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54 def NAME#64rm
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55 :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
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56 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
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57 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
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58 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
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59 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
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60 } // end multiclass
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61
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62
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63 // Conditional Moves.
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64 defm CMOVO : CMOV<0x40, "cmovo" , X86_COND_O>;
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65 defm CMOVNO : CMOV<0x41, "cmovno", X86_COND_NO>;
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66 defm CMOVB : CMOV<0x42, "cmovb" , X86_COND_B>;
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67 defm CMOVAE : CMOV<0x43, "cmovae", X86_COND_AE>;
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68 defm CMOVE : CMOV<0x44, "cmove" , X86_COND_E>;
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69 defm CMOVNE : CMOV<0x45, "cmovne", X86_COND_NE>;
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70 defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>;
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71 defm CMOVA : CMOV<0x47, "cmova" , X86_COND_A>;
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72 defm CMOVS : CMOV<0x48, "cmovs" , X86_COND_S>;
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73 defm CMOVNS : CMOV<0x49, "cmovns", X86_COND_NS>;
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74 defm CMOVP : CMOV<0x4A, "cmovp" , X86_COND_P>;
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75 defm CMOVNP : CMOV<0x4B, "cmovnp", X86_COND_NP>;
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76 defm CMOVL : CMOV<0x4C, "cmovl" , X86_COND_L>;
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77 defm CMOVGE : CMOV<0x4D, "cmovge", X86_COND_GE>;
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78 defm CMOVLE : CMOV<0x4E, "cmovle", X86_COND_LE>;
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79 defm CMOVG : CMOV<0x4F, "cmovg" , X86_COND_G>;
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80
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81
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82 // SetCC instructions.
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83 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
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84 let Uses = [EFLAGS] in {
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85 def r : I<opc, MRMXr, (outs GR8:$dst), (ins),
0
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86 !strconcat(Mnemonic, "\t$dst"),
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87 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
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88 IIC_SET_R>, TB, Sched<[WriteALU]>;
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89 def m : I<opc, MRMXm, (outs), (ins i8mem:$dst),
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90 !strconcat(Mnemonic, "\t$dst"),
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91 [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
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92 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
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93 } // Uses = [EFLAGS]
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94 }
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95
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96 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
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97 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
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98 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
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99 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
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100 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
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101 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
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102 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
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103 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
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104 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
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105 defm SETNS : SETCC<0x99, "setns", X86_COND_NS>; // is not signed
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106 defm SETP : SETCC<0x9A, "setp", X86_COND_P>; // is parity bit set
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107 defm SETNP : SETCC<0x9B, "setnp", X86_COND_NP>; // is parity bit not set
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108 defm SETL : SETCC<0x9C, "setl", X86_COND_L>; // signed less than
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109 defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>; // signed greater or equal
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110 defm SETLE : SETCC<0x9E, "setle", X86_COND_LE>; // signed less than or equal
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111 defm SETG : SETCC<0x9F, "setg", X86_COND_G>; // signed greater than
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112