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annotate lib/Target/X86/X86SchedSandyBridge.td @ 116:a609e5c42ecc

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change from CGF to this
author mir3636
date Mon, 08 Aug 2016 19:47:00 +0900
parents 60c9769439b8
children 803732b1fca8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the machine model for Sandy Bridge to support instruction
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11 // scheduling and other instruction cost heuristics.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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15 def SandyBridgeModel : SchedMachineModel {
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16 // All x86 instructions are modeled as a single micro-op, and SB can decode 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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17 // instructions per cycle.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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18 // FIXME: Identify instructions that aren't a single fused micro-op.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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19 let IssueWidth = 4;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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20 let MicroOpBufferSize = 168; // Based on the reorder buffer.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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21 let LoadLatency = 4;
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22 let MispredictPenalty = 16;
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23
77
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24 // Based on the LSD (loop-stream detector) queue size.
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25 let LoopMicroOpBufferSize = 28;
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26
0
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27 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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28 // the scheduler to assign a default model to unrecognized opcodes.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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29 let CompleteModel = 0;
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30 }
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31
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32 let SchedModel = SandyBridgeModel in {
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33
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34 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
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35
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36 // Ports 0, 1, and 5 handle all computation.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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37 def SBPort0 : ProcResource<1>;
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38 def SBPort1 : ProcResource<1>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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39 def SBPort5 : ProcResource<1>;
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40
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41 // Ports 2 and 3 are identical. They handle loads and the address half of
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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42 // stores.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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43 def SBPort23 : ProcResource<2>;
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44
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45 // Port 4 gets the data half of stores. Store data can be available later than
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46 // the store address, but since we don't model the latency of stores, we can
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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47 // ignore that.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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48 def SBPort4 : ProcResource<1>;
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49
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50 // Many micro-ops are capable of issuing on multiple ports.
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parents:
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51 def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>;
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52 def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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53 def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
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parents:
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54
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55 // 54 Entry Unified Scheduler
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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56 def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> {
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57 let BufferSize=54;
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58 }
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parents:
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59
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60 // Integer division issued on port 0.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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61 def SBDivider : ProcResource<1>;
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62
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63 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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64 // cycles after the memory operand.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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65 def : ReadAdvance<ReadAfterLd, 4>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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66
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67 // Many SchedWrites are defined in pairs with and without a folded load.
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parents:
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68 // Instructions with folded loads are usually micro-fused, so they only appear
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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69 // as two micro-ops when queued in the reservation station.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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70 // This multiclass defines the resource usage for variants with and without
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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71 // folded loads.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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72 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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73 ProcResourceKind ExePort,
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parents:
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74 int Lat> {
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parents:
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75 // Register variant is using a single cycle on ExePort.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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76 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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77
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78 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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79 // latency.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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80 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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81 let Latency = !add(Lat, 4);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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82 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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83 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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84
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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85 // A folded store needs a cycle on port 4 for the store data, but it does not
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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86 // need an extra port 2/3 cycle to recompute the address.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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87 def : WriteRes<WriteRMW, [SBPort4]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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88
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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89 def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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90 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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91 def : WriteRes<WriteMove, [SBPort015]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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92 def : WriteRes<WriteZero, []>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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93
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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94 defm : SBWriteResPair<WriteALU, SBPort015, 1>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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95 defm : SBWriteResPair<WriteIMul, SBPort1, 3>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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96 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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97 defm : SBWriteResPair<WriteShift, SBPort05, 1>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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98 defm : SBWriteResPair<WriteJump, SBPort5, 1>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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99
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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100 // This is for simple LEAs with one or two input operands.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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101 // The complex ones can only execute on port 1, and they require two cycles on
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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102 // the port to read all inputs. We don't model that.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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103 def : WriteRes<WriteLEA, [SBPort15]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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104
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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105 // This is quite rough, latency depends on the dividend.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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106 def : WriteRes<WriteIDiv, [SBPort0, SBDivider]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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107 let Latency = 25;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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108 let ResourceCycles = [1, 10];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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109 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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110 def : WriteRes<WriteIDivLd, [SBPort23, SBPort0, SBDivider]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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111 let Latency = 29;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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112 let ResourceCycles = [1, 1, 10];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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113 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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114
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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115 // Scalar and vector floating point.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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116 defm : SBWriteResPair<WriteFAdd, SBPort1, 3>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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117 defm : SBWriteResPair<WriteFMul, SBPort0, 5>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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118 defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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119 defm : SBWriteResPair<WriteFRcp, SBPort0, 5>;
83
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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120 defm : SBWriteResPair<WriteFRsqrt, SBPort0, 5>;
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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121 defm : SBWriteResPair<WriteFSqrt, SBPort0, 15>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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122 defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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123 defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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124 defm : SBWriteResPair<WriteCvtF2F, SBPort1, 3>;
77
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parents: 0
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125 defm : SBWriteResPair<WriteFShuffle, SBPort5, 1>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
126 defm : SBWriteResPair<WriteFBlend, SBPort05, 1>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
127 def : WriteRes<WriteFVarBlend, [SBPort0, SBPort5]> {
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parents: 0
diff changeset
128 let Latency = 2;
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parents: 0
diff changeset
129 let ResourceCycles = [1, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
130 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
131 def : WriteRes<WriteFVarBlendLd, [SBPort0, SBPort5, SBPort23]> {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
132 let Latency = 6;
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parents: 0
diff changeset
133 let ResourceCycles = [1, 1, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
134 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
135
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
136 // Vector integer operations.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
137 defm : SBWriteResPair<WriteVecShift, SBPort05, 1>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
138 defm : SBWriteResPair<WriteVecLogic, SBPort015, 1>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
139 defm : SBWriteResPair<WriteVecALU, SBPort15, 1>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
140 defm : SBWriteResPair<WriteVecIMul, SBPort0, 5>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
141 defm : SBWriteResPair<WriteShuffle, SBPort15, 1>;
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
142 defm : SBWriteResPair<WriteBlend, SBPort15, 1>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
143 def : WriteRes<WriteVarBlend, [SBPort1, SBPort5]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
144 let Latency = 2;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
145 let ResourceCycles = [1, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
146 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
147 def : WriteRes<WriteVarBlendLd, [SBPort1, SBPort5, SBPort23]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
148 let Latency = 6;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
149 let ResourceCycles = [1, 1, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
150 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
151 def : WriteRes<WriteMPSAD, [SBPort0, SBPort1, SBPort5]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
152 let Latency = 6;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
153 let ResourceCycles = [1, 1, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
154 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
155 def : WriteRes<WriteMPSADLd, [SBPort0, SBPort1, SBPort5, SBPort23]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
156 let Latency = 6;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
157 let ResourceCycles = [1, 1, 1, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
158 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
159
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
160 // String instructions.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
161 // Packed Compare Implicit Length Strings, Return Mask
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
162 def : WriteRes<WritePCmpIStrM, [SBPort015]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
163 let Latency = 11;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
164 let ResourceCycles = [3];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
165 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
166 def : WriteRes<WritePCmpIStrMLd, [SBPort015, SBPort23]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
167 let Latency = 11;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
168 let ResourceCycles = [3, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
169 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
170
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
171 // Packed Compare Explicit Length Strings, Return Mask
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
172 def : WriteRes<WritePCmpEStrM, [SBPort015]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
173 let Latency = 11;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
174 let ResourceCycles = [8];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
175 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
176 def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
177 let Latency = 11;
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parents: 0
diff changeset
178 let ResourceCycles = [7, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
179 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
180
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parents: 0
diff changeset
181 // Packed Compare Implicit Length Strings, Return Index
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
182 def : WriteRes<WritePCmpIStrI, [SBPort015]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
183 let Latency = 3;
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parents: 0
diff changeset
184 let ResourceCycles = [3];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
185 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
186 def : WriteRes<WritePCmpIStrILd, [SBPort015, SBPort23]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
187 let Latency = 3;
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parents: 0
diff changeset
188 let ResourceCycles = [3, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
189 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
190
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
191 // Packed Compare Explicit Length Strings, Return Index
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
192 def : WriteRes<WritePCmpEStrI, [SBPort015]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
193 let Latency = 4;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
194 let ResourceCycles = [8];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
195 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
196 def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
197 let Latency = 4;
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parents: 0
diff changeset
198 let ResourceCycles = [7, 1];
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parents: 0
diff changeset
199 }
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parents: 0
diff changeset
200
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
201 // AES Instructions.
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parents: 0
diff changeset
202 def : WriteRes<WriteAESDecEnc, [SBPort015]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
203 let Latency = 8;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
204 let ResourceCycles = [2];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
205 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
206 def : WriteRes<WriteAESDecEncLd, [SBPort015, SBPort23]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
207 let Latency = 8;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
208 let ResourceCycles = [2, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
209 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
210
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
211 def : WriteRes<WriteAESIMC, [SBPort015]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
212 let Latency = 8;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
213 let ResourceCycles = [2];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
214 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
215 def : WriteRes<WriteAESIMCLd, [SBPort015, SBPort23]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
216 let Latency = 8;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
217 let ResourceCycles = [2, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
218 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
219
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
220 def : WriteRes<WriteAESKeyGen, [SBPort015]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
221 let Latency = 8;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
222 let ResourceCycles = [11];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
223 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
224 def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
225 let Latency = 8;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
226 let ResourceCycles = [10, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
227 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
228
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
229 // Carry-less multiplication instructions.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
230 def : WriteRes<WriteCLMul, [SBPort015]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
231 let Latency = 14;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
232 let ResourceCycles = [18];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
233 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
234 def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
235 let Latency = 14;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
236 let ResourceCycles = [17, 1];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
237 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
238
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
239
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
240 def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
241 def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
77
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
242 def : WriteRes<WriteFence, [SBPort23, SBPort4]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
243 def : WriteRes<WriteNop, []>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
244
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
245 // AVX2 is not supported on that architecture, but we should define the basic
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
246 // scheduling resources anyway.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
247 defm : SBWriteResPair<WriteFShuffle256, SBPort0, 1>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
248 defm : SBWriteResPair<WriteShuffle256, SBPort0, 1>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
249 defm : SBWriteResPair<WriteVarVecShift, SBPort0, 1>;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
250 } // SchedModel