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annotate test/CodeGen/AMDGPU/literals.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents test/CodeGen/R600/literals.ll@60c9769439b8
children 7d135dc70f03
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1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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2
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3 ; Test using an integer literal constant.
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4 ; Generated ASM should be:
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5 ; ADD_INT KC0[2].Z literal.x, 5
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6 ; or
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7 ; ADD_INT literal.x KC0[2].Z, 5
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8
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9 ; CHECK: {{^}}i32_literal:
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10 ; CHECK: ADD_INT {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
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11 ; CHECK-NEXT: LSHR
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12 ; CHECK-NEXT: 5
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13 define void @i32_literal(i32 addrspace(1)* %out, i32 %in) {
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14 entry:
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15 %0 = add i32 5, %in
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16 store i32 %0, i32 addrspace(1)* %out
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17 ret void
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18 }
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19
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20 ; Test using a float literal constant.
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21 ; Generated ASM should be:
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22 ; ADD KC0[2].Z literal.x, 5.0
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23 ; or
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24 ; ADD literal.x KC0[2].Z, 5.0
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25
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26 ; CHECK: {{^}}float_literal:
0
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27 ; CHECK: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
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28 ; CHECK-NEXT: LSHR
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29 ; CHECK-NEXT: 1084227584(5.0
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30 define void @float_literal(float addrspace(1)* %out, float %in) {
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31 entry:
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32 %0 = fadd float 5.0, %in
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33 store float %0, float addrspace(1)* %out
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34 ret void
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35 }
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36
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37 ; Make sure inline literals are folded into REG_SEQUENCE instructions.
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38 ; CHECK: {{^}}inline_literal_reg_sequence:
0
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39 ; CHECK: MOV {{\** *}}T[[GPR:[0-9]]].X, 0.0
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40 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Y, 0.0
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41 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0
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42 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0
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43
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44 define void @inline_literal_reg_sequence(<4 x i32> addrspace(1)* %out) {
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45 entry:
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46 store <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> addrspace(1)* %out
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47 ret void
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48 }
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49
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50 ; CHECK: {{^}}inline_literal_dot4:
0
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51 ; CHECK: DOT4 T[[GPR:[0-9]]].X, 1.0
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52 ; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0
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53 ; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0
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54 ; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0
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55 define void @inline_literal_dot4(float addrspace(1)* %out) {
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56 entry:
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57 %0 = call float @llvm.AMDGPU.dp4(<4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)
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58 store float %0, float addrspace(1)* %out
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59 ret void
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60 }
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61
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62 declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
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63
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64 attributes #1 = { readnone }