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83
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1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -o - %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s
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3
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4 ; SI-LABEL:{{^}}row_filter_C1_D0:
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5 ; SI: s_endpgm
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6 ; Function Attrs: nounwind
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7 define void @row_filter_C1_D0() {
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8 entry:
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9 br i1 undef, label %for.inc.1, label %do.body.preheader
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10
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11 do.body.preheader: ; preds = %entry
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12 %0 = insertelement <4 x i32> zeroinitializer, i32 undef, i32 1
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13 br i1 undef, label %do.body56.1, label %do.body90
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14
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15 do.body90: ; preds = %do.body56.2, %do.body56.1, %do.body.preheader
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16 %1 = phi <4 x i32> [ %6, %do.body56.2 ], [ %5, %do.body56.1 ], [ %0, %do.body.preheader ]
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17 %2 = insertelement <4 x i32> %1, i32 undef, i32 2
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18 %3 = insertelement <4 x i32> %2, i32 undef, i32 3
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19 br i1 undef, label %do.body124.1, label %do.body.1562.preheader
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20
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21 do.body.1562.preheader: ; preds = %do.body124.1, %do.body90
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22 %storemerge = phi <4 x i32> [ %3, %do.body90 ], [ %7, %do.body124.1 ]
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23 %4 = insertelement <4 x i32> undef, i32 undef, i32 1
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24 br label %for.inc.1
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25
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26 do.body56.1: ; preds = %do.body.preheader
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27 %5 = insertelement <4 x i32> %0, i32 undef, i32 1
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28 %or.cond472.1 = or i1 undef, undef
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29 br i1 %or.cond472.1, label %do.body56.2, label %do.body90
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30
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31 do.body56.2: ; preds = %do.body56.1
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32 %6 = insertelement <4 x i32> %5, i32 undef, i32 1
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33 br label %do.body90
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34
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35 do.body124.1: ; preds = %do.body90
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36 %7 = insertelement <4 x i32> %3, i32 undef, i32 3
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37 br label %do.body.1562.preheader
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38
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39 for.inc.1: ; preds = %do.body.1562.preheader, %entry
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40 %storemerge591 = phi <4 x i32> [ zeroinitializer, %entry ], [ %storemerge, %do.body.1562.preheader ]
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41 %add.i495 = add <4 x i32> %storemerge591, undef
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42 unreachable
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43 }
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44
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45 ; SI-LABEL: {{^}}foo:
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46 ; SI: s_endpgm
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47 define void @foo() #0 {
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48 bb:
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49 br i1 undef, label %bb2, label %bb1
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50
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51 bb1: ; preds = %bb
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52 br i1 undef, label %bb4, label %bb6
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53
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54 bb2: ; preds = %bb4, %bb
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55 %tmp = phi float [ %tmp5, %bb4 ], [ 0.000000e+00, %bb ]
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56 br i1 undef, label %bb9, label %bb13
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57
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58 bb4: ; preds = %bb7, %bb6, %bb1
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59 %tmp5 = phi float [ undef, %bb1 ], [ undef, %bb6 ], [ %tmp8, %bb7 ]
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60 br label %bb2
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61
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62 bb6: ; preds = %bb1
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63 br i1 undef, label %bb7, label %bb4
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64
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65 bb7: ; preds = %bb6
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66 %tmp8 = fmul float undef, undef
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67 br label %bb4
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68
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69 bb9: ; preds = %bb2
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70 %tmp10 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 2)
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71 %tmp11 = extractelement <4 x float> %tmp10, i32 1
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72 %tmp12 = extractelement <4 x float> %tmp10, i32 3
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73 br label %bb14
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74
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75 bb13: ; preds = %bb2
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76 br i1 undef, label %bb23, label %bb24
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77
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78 bb14: ; preds = %bb27, %bb24, %bb9
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79 %tmp15 = phi float [ %tmp12, %bb9 ], [ undef, %bb27 ], [ 0.000000e+00, %bb24 ]
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80 %tmp16 = phi float [ %tmp11, %bb9 ], [ undef, %bb27 ], [ %tmp25, %bb24 ]
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81 %tmp17 = fmul float 10.5, %tmp16
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82 %tmp18 = fmul float 11.5, %tmp15
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83 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp18, float %tmp17, float %tmp17, float %tmp17)
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84 ret void
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85
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86 bb23: ; preds = %bb13
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87 br i1 undef, label %bb24, label %bb26
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88
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89 bb24: ; preds = %bb26, %bb23, %bb13
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90 %tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.000000e+00, %bb23 ]
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91 br i1 undef, label %bb27, label %bb14
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92
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93 bb26: ; preds = %bb23
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94 br label %bb24
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95
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96 bb27: ; preds = %bb24
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97 br label %bb14
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98 }
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99
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100 ; Function Attrs: nounwind readnone
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101 declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
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102
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103 ; Function Attrs: nounwind readnone
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104 declare i32 @llvm.SI.packf16(float, float) #1
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105
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106 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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107
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108 attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" }
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109 attributes #1 = { nounwind readnone }
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