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annotate test/CodeGen/ARM/2011-08-29-SchedCycle.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 95c75e76d11b
children
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1 ; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -o -
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2
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3 ; When a i64 sub is expanded to subc + sube.
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4 ; libcall #1
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5 ; \
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6 ; \ subc
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7 ; \ / \
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8 ; \ / \
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9 ; \ / libcall #2
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10 ; sube
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11 ;
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12 ; If the libcalls are not serialized (i.e. both have chains which are dag
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13 ; entry), legalizer can serialize them in arbitrary orders. If it's
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14 ; unlucky, it can force libcall #2 before libcall #1 in the above case.
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15 ;
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16 ; subc
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17 ; |
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18 ; libcall #2
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19 ; |
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20 ; libcall #1
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21 ; |
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22 ; sube
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23 ;
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24 ; However since subc and sube are "glued" together, this ends up being a
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25 ; cycle when the scheduler combine subc and sube as a single scheduling
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26 ; unit.
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27 ;
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28 ; The right solution is to fix LegalizeType too chains the libcalls together.
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29 ; However, LegalizeType is not processing nodes in order. The fix now is to
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30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
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31 ; rdar://10019576
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32
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33 define void @t() nounwind {
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34 entry:
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35 %tmp = load i64, i64* undef, align 4
0
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36 %tmp5 = udiv i64 %tmp, 30
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37 %tmp13 = and i64 %tmp5, 64739244643450880
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38 %tmp16 = sub i64 0, %tmp13
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39 %tmp19 = and i64 %tmp16, 63
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40 %tmp20 = urem i64 %tmp19, 3
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41 %tmp22 = and i64 %tmp16, -272346829004752
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42 store i64 %tmp22, i64* undef, align 4
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43 store i64 %tmp20, i64* undef, align 4
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44 ret void
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45 }