annotate test/CodeGen/X86/sse-domains.ll @ 33:e4204d083e25

LLVM 3.5
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 14:32:10 +0900
parents 95c75e76d11b
children 60c9769439b8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -mcpu=nehalem | FileCheck %s
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2 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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3 target triple = "x86_64-apple-macosx10.7"
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4
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5 ; CHECK: f
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6 ;
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7 ; This function contains load / store / and operations that all can execute in
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8 ; any domain. The only domain-specific operation is the %add = shl... operation
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9 ; which is <4 x i32>.
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10 ;
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11 ; The paddd instruction can only influence the other operations through the loop
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12 ; back-edge. Check that everything is still moved into the integer domain.
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13
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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14 define void @f(<4 x i32>* nocapture %p, i32 %n) nounwind uwtable ssp {
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15 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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16 br label %while.body
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17
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18 ; Materialize a zeroinitializer and a constant-pool load in the integer domain.
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19 ; The order is not important.
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20 ; CHECK: pxor
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21 ; CHECK: movdqa
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22
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23 ; The instructions in the loop must all be integer domain as well.
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24 ; CHECK: while.body
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25 ; CHECK: pand
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26 ; CHECK: movdqa
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27 ; CHECK: movdqa
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28 ; Finally, the controlling integer-only instruction.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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29 ; CHECK: paddd
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30 while.body:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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31 %p.addr.04 = phi <4 x i32>* [ %incdec.ptr, %while.body ], [ %p, %entry ]
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32 %n.addr.03 = phi i32 [ %dec, %while.body ], [ %n, %entry ]
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33 %x.02 = phi <4 x i32> [ %add, %while.body ], [ zeroinitializer, %entry ]
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34 %dec = add nsw i32 %n.addr.03, -1
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35 %and = and <4 x i32> %x.02, <i32 127, i32 127, i32 127, i32 127>
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36 %incdec.ptr = getelementptr inbounds <4 x i32>* %p.addr.04, i64 1
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37 store <4 x i32> %and, <4 x i32>* %p.addr.04, align 16
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38 %0 = load <4 x i32>* %incdec.ptr, align 16
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39 %add = shl <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>
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40 %tobool = icmp eq i32 %dec, 0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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41 br i1 %tobool, label %while.end, label %while.body
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42
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43 while.end:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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44 ret void
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45 }
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46
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47 ; CHECK: f2
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48 ; CHECK: for.body
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49 ;
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50 ; This loop contains two cvtsi2ss instructions that update the same xmm
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51 ; register. Verify that the execution dependency fix pass breaks those
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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52 ; dependencies by inserting xorps instructions.
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53 ;
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54 ; If the register allocator chooses different registers for the two cvtsi2ss
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55 ; instructions, they are still dependent on themselves.
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56 ; CHECK: xorps [[XMM1:%xmm[0-9]+]]
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57 ; CHECK: , [[XMM1]]
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58 ; CHECK: cvtsi2ssl %{{.*}}, [[XMM1]]
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59 ; CHECK: xorps [[XMM2:%xmm[0-9]+]]
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60 ; CHECK: , [[XMM2]]
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61 ; CHECK: cvtsi2ssl %{{.*}}, [[XMM2]]
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62 ;
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63 define float @f2(i32 %m) nounwind uwtable readnone ssp {
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64 entry:
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65 %tobool3 = icmp eq i32 %m, 0
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66 br i1 %tobool3, label %for.end, label %for.body
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67
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68 for.body: ; preds = %entry, %for.body
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69 %m.addr.07 = phi i32 [ %dec, %for.body ], [ %m, %entry ]
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70 %s1.06 = phi float [ %add, %for.body ], [ 0.000000e+00, %entry ]
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71 %s2.05 = phi float [ %add2, %for.body ], [ 0.000000e+00, %entry ]
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72 %n.04 = phi i32 [ %inc, %for.body ], [ 1, %entry ]
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73 %conv = sitofp i32 %n.04 to float
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74 %add = fadd float %s1.06, %conv
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75 %conv1 = sitofp i32 %m.addr.07 to float
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76 %add2 = fadd float %s2.05, %conv1
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77 %inc = add nsw i32 %n.04, 1
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78 %dec = add nsw i32 %m.addr.07, -1
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79 %tobool = icmp eq i32 %dec, 0
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80 br i1 %tobool, label %for.end, label %for.body
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81
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82 for.end: ; preds = %for.body, %entry
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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83 %s1.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
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84 %s2.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add2, %for.body ]
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85 %sub = fsub float %s1.0.lcssa, %s2.0.lcssa
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86 ret float %sub
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87 }