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1 ; RUN: llc < %s | FileCheck %s
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2
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3 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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4 target triple = "aarch64-unknown-linux-gnu"
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5
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6 define <4 x i16> @f(<4 x i32> %vqdmlal_v3.i, <8 x i16> %x5) {
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7 entry:
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8 ; Check that we don't just dup the input vector. The code emitted is ext, dup, ext, ext
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9 ; but only match the last three instructions as the first two could be combined to
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10 ; a dup2 at some stage.
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11 ; CHECK: dup
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12 ; CHECK: ext
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13 ; CHECK: ext
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14 %x4 = extractelement <4 x i32> %vqdmlal_v3.i, i32 2
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15 %vgetq_lane = trunc i32 %x4 to i16
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16 %vecinit.i = insertelement <4 x i16> undef, i16 %vgetq_lane, i32 0
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17 %vecinit2.i = insertelement <4 x i16> %vecinit.i, i16 %vgetq_lane, i32 2
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18 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vgetq_lane, i32 3
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19 %vgetq_lane261 = extractelement <8 x i16> %x5, i32 0
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20 %vset_lane267 = insertelement <4 x i16> %vecinit3.i, i16 %vgetq_lane261, i32 1
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21 ret <4 x i16> %vset_lane267
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22 }
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